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sbourdeauducqsbourdeauducq
committedDec 2, 2016
drtio: support different configurations and speeds
·
8.03.0
1 parent 3931d80 commit 6353f6d

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3 files changed

+107
-22
lines changed

3 files changed

+107
-22
lines changed
 

‎artiq/gateware/drtio/transceiver/gtx_7series.py

+12-5
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,10 @@
77
from artiq.gateware.drtio.transceiver.gtx_7series_init import *
88

99

10-
class GTX_1000BASE_BX10(Module):
11-
rtio_clk_freq = 62.5e6
12-
13-
# The transceiver clock on clock_pads must be 62.5MHz
14-
# when clock_div2=False, and 125MHz when clock_div2=True.
10+
class GTX_20X(Module):
11+
# The transceiver clock on clock_pads must be at the RTIO clock
12+
# frequency when clock_div2=False, and 2x that frequency when
13+
# clock_div2=True.
1514
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
1615
clock_div2=False):
1716
self.submodules.encoder = ClockDomainsRenamer("rtio")(
@@ -192,6 +191,14 @@ def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
192191
]
193192

194193

194+
class GTX_1000BASE_BX10(GTX_20X):
195+
rtio_clk_freq = 62.5e6
196+
197+
198+
class GTX_3G(GTX_20X):
199+
rtio_clk_freq = 150e6
200+
201+
195202
class RXSynchronizer(Module, AutoCSR):
196203
"""Delays the data received in the rtio_rx by a configurable amount
197204
so that it meets s/h in the rtio domain, and recapture it in the rtio

‎artiq/gateware/targets/kc705_drtio_master.py

+47-9
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
import argparse
44

55
from migen import *
6+
from migen.build.generic_platform import *
67

78
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
89
from misoc.integration.builder import builder_args, builder_argdict
@@ -15,6 +16,14 @@
1516
from artiq import __version__ as artiq_version
1617

1718

19+
fmc_clock_io = [
20+
("ad9154_refclk", 0,
21+
Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
22+
Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
23+
)
24+
]
25+
26+
1827
class Master(MiniSoC, AMPSoC):
1928
mem_map = {
2029
"timer_kernel": 0x10000000,
@@ -24,7 +33,7 @@ class Master(MiniSoC, AMPSoC):
2433
}
2534
mem_map.update(MiniSoC.mem_map)
2635

27-
def __init__(self, **kwargs):
36+
def __init__(self, cfg, medium, **kwargs):
2837
MiniSoC.__init__(self,
2938
cpu_type="or1k",
3039
sdram_controller_type="minicon",
@@ -36,13 +45,36 @@ def __init__(self, **kwargs):
3645

3746
platform = self.platform
3847

39-
self.comb += platform.request("sfp_tx_disable_n").eq(1)
40-
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
41-
clock_pads=platform.request("sgmii_clock"),
42-
tx_pads=platform.request("sfp_tx"),
43-
rx_pads=platform.request("sfp_rx"),
44-
sys_clk_freq=self.clk_freq,
45-
clock_div2=True)
48+
if medium == "sfp":
49+
self.comb += platform.request("sfp_tx_disable_n").eq(1)
50+
tx_pads = platform.request("sfp_tx")
51+
rx_pads = platform.request("sfp_rx")
52+
elif medium == "sma":
53+
tx_pads = platform.request("user_sma_mgt_tx")
54+
rx_pads = platform.request("user_sma_mgt_rx")
55+
else:
56+
raise ValueError
57+
58+
if cfg == "simple_gbe":
59+
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
60+
# simple TTLs
61+
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
62+
clock_pads=platform.request("sgmii_clock"),
63+
tx_pads=tx_pads,
64+
rx_pads=rx_pads,
65+
sys_clk_freq=self.clk_freq,
66+
clock_div2=True)
67+
elif cfg == "sawg_3g":
68+
# 3Gb link, 150MHz RTIO clock
69+
# with SAWG on local RTIO and AD9154-FMC-EBZ
70+
platform.register_extension(fmc_clock_io)
71+
self.submodules.transceiver = gtx_7series.GTX_3G(
72+
clock_pads=platform.request("ad9154_refclk"),
73+
tx_pads=tx_pads,
74+
rx_pads=rx_pads,
75+
sys_clk_freq=self.clk_freq)
76+
else:
77+
raise ValueError
4678
self.submodules.drtio = DRTIOMaster(self.transceiver)
4779
self.csr_devices.append("drtio")
4880

@@ -71,9 +103,15 @@ def main():
71103
description="ARTIQ with DRTIO on KC705 - Master")
72104
builder_args(parser)
73105
soc_kc705_args(parser)
106+
parser.add_argument("-c", "--config", default="simple_gbe",
107+
help="configuration: simple_gbe/sawg_3g "
108+
"(default: %(default)s)")
109+
parser.add_argument("--medium", default="sfp",
110+
help="medium to use for transceiver link: sfp/sma "
111+
"(default: %(default)s)")
74112
args = parser.parse_args()
75113

76-
soc = Master(**soc_kc705_argdict(args))
114+
soc = Master(args.config, args.medium, **soc_kc705_argdict(args))
77115
build_artiq_soc(soc, builder_argdict(args))
78116

79117

‎artiq/gateware/targets/kc705_drtio_satellite.py

+48-8
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
import argparse
22

33
from migen import *
4+
from migen.build.generic_platform import *
45
from migen.build.platforms import kc705
56

67
from misoc.cores.i2c import *
@@ -12,6 +13,7 @@
1213
from artiq.gateware.drtio import DRTIOSatellite
1314

1415

16+
# TODO: parameters for sawg_3g
1517
def get_i2c_program(sys_clk_freq):
1618
# NOTE: the logical parameters DO NOT MAP to physical values written
1719
# into registers. They have to be mapped; see the datasheet.
@@ -111,8 +113,16 @@ def __init__(self, platform, sys_clk_freq):
111113
)
112114

113115

116+
fmc_clock_io = [
117+
("ad9154_refclk", 0,
118+
Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
119+
Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
120+
)
121+
]
122+
123+
114124
class Satellite(Module):
115-
def __init__(self, toolchain="vivado"):
125+
def __init__(self, cfg, medium, toolchain):
116126
self.platform = platform = kc705.Platform(toolchain=toolchain)
117127

118128
rtio_channels = []
@@ -141,12 +151,36 @@ def __init__(self, toolchain="vivado"):
141151
sequencer.reset.eq(si5324_reset_clock.si5324_not_ready)
142152
]
143153

144-
self.comb += platform.request("sfp_tx_disable_n").eq(1)
145-
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
146-
clock_pads=platform.request("si5324_clkout"),
147-
tx_pads=platform.request("sfp_tx"),
148-
rx_pads=platform.request("sfp_rx"),
149-
sys_clk_freq=sys_clk_freq)
154+
if medium == "sfp":
155+
self.comb += platform.request("sfp_tx_disable_n").eq(1)
156+
tx_pads = platform.request("sfp_tx")
157+
rx_pads = platform.request("sfp_rx")
158+
elif medium == "sma":
159+
tx_pads = platform.request("user_sma_mgt_tx")
160+
rx_pads = platform.request("user_sma_mgt_rx")
161+
else:
162+
raise ValueError
163+
164+
if cfg == "simple_gbe":
165+
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
166+
# simple TTLs
167+
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
168+
clock_pads=platform.request("sgmii_clock"),
169+
tx_pads=tx_pads,
170+
rx_pads=rx_pads,
171+
sys_clk_freq=sys_clk_freq,
172+
clock_div2=True)
173+
elif cfg == "sawg_3g":
174+
# 3Gb link, 150MHz RTIO clock
175+
# with SAWG on local RTIO and AD9154-FMC-EBZ
176+
platform.register_extension(fmc_clock_io)
177+
self.submodules.transceiver = gtx_7series.GTX_3G(
178+
clock_pads=platform.request("ad9154_refclk"),
179+
tx_pads=tx_pads,
180+
rx_pads=rx_pads,
181+
sys_clk_freq=sys_clk_freq)
182+
else:
183+
raise ValueError
150184
self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
151185
self.transceiver.rtio_clk_freq)
152186
self.submodules.drtio = DRTIOSatellite(
@@ -163,9 +197,15 @@ def main():
163197
parser.add_argument("--output-dir", default="drtiosat_kc705",
164198
help="output directory for generated "
165199
"source files and binaries")
200+
parser.add_argument("-c", "--config", default="simple_gbe",
201+
help="configuration: simple_gbe/sawg_3g "
202+
"(default: %(default)s)")
203+
parser.add_argument("--medium", default="sfp",
204+
help="medium to use for transceiver link: sfp/sma "
205+
"(default: %(default)s)")
166206
args = parser.parse_args()
167207

168-
top = Satellite(args.toolchain)
208+
top = Satellite(args.config, args.medium, args.toolchain)
169209
top.build(build_dir=args.output_dir)
170210

171211
if __name__ == "__main__":

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