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drtio: fix transmit datapath with transceiver width > max packet width
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sbourdeauducq committed Nov 27, 2016
1 parent b2450c7 commit 046b8bf
Showing 1 changed file with 24 additions and 12 deletions.
36 changes: 24 additions & 12 deletions artiq/gateware/drtio/rt_packets.py
Original file line number Diff line number Diff line change
@@ -140,7 +140,7 @@ def __init__(self, frame, data, plm):
self.packet_buffer = Signal(max(layout_len(l)
for l in plm.layouts.values()))
w_in_packet = len(self.packet_buffer)//ws
self.packet_last_n = Signal(max=w_in_packet)
self.packet_last_n = Signal(max=max(w_in_packet, 2))
self.packet_stb = Signal()
self.packet_last = Signal()

@@ -149,18 +149,30 @@ def __init__(self, frame, data, plm):

# # #

packet_buffer_count = Signal(max=w_in_packet)
self.comb += self.packet_last.eq(packet_buffer_count == self.packet_last_n)
self.sync += frame.eq(0)

if w_in_packet > 1:
packet_buffer_count = Signal(max=w_in_packet)
self.comb += self.packet_last.eq(packet_buffer_count == self.packet_last_n)
self.sync += [
packet_buffer_count.eq(0),
If(self.packet_stb,
frame.eq(1),
Case(packet_buffer_count,
{i: data.eq(self.packet_buffer[i*ws:(i+1)*ws])
for i in range(w_in_packet)}),
packet_buffer_count.eq(packet_buffer_count + 1)
)
]
else:
self.comb += self.packet_last.eq(1)
self.sync += \
If(self.packet_stb,
frame.eq(1),
data.eq(self.packet_buffer)
)

self.sync += [
frame.eq(0),
packet_buffer_count.eq(0),
If(self.packet_stb,
frame.eq(1),
Case(packet_buffer_count,
{i: data.eq(self.packet_buffer[i*ws:(i+1)*ws])
for i in range(w_in_packet)}),
packet_buffer_count.eq(packet_buffer_count + 1)
),
If(self.raw_stb,
frame.eq(1),
data.eq(self.raw_data)

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