Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/artiq
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 8090abef5d4f
Choose a base ref
...
head repository: m-labs/artiq
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: b2450c7c56aa
Choose a head ref
  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Nov 25, 2016

  1. Copy the full SHA
    d381dd5 View commit details

Commits on Nov 26, 2016

  1. drtio: large data fixes

    sbourdeauducq committed Nov 26, 2016
    Copy the full SHA
    0903964 View commit details

Commits on Nov 27, 2016

  1. drtio: test large data

    sbourdeauducq committed Nov 27, 2016
    Copy the full SHA
    b2450c7 View commit details
Showing with 36 additions and 11 deletions.
  1. +7 −4 artiq/gateware/drtio/rt_packets.py
  2. +29 −7 artiq/test/gateware/drtio/test_full_stack.py
11 changes: 7 additions & 4 deletions artiq/gateware/drtio/rt_packets.py
Original file line number Diff line number Diff line change
@@ -231,7 +231,7 @@ def __init__(self, link_layer):
self.sync += \
If(write_data_buffer_load,
Case(write_data_buffer_cnt,
{i: write_data_buffer[i*ws:(i+1)*ws].eq(link_layer.rx_rt_data)
{i: write_data_buffer[i*ws:(i+1)*ws].eq(rx_dp.data_r)
for i in range(512//ws)}),
write_data_buffer_cnt.eq(write_data_buffer_cnt + 1)
).Else(
@@ -515,11 +515,14 @@ def __init__(self, link_layer, write_fifo_depth=4):
write_data.eq(write_data_d))

short_data_len = tx_plm.field_length("write", "short_data")
write_extra_data = Signal(512)
self.comb += write_extra_data.eq(write_data[short_data_len:])
write_extra_data_d = Signal(512)
self.comb += write_extra_data_d.eq(write_data_d[short_data_len:])
for i in range(512//ws):
self.sync.rtio += If(wfifo.re,
If(write_extra_data[ws*i:ws*(i+1)] != 0, write_extra_data_cnt.eq(i+1)))
If(write_extra_data_d[ws*i:ws*(i+1)] != 0, write_extra_data_cnt.eq(i+1)))

write_extra_data = Signal(512)
self.sync.rtio += If(wfifo.re, write_extra_data.eq(write_extra_data_d))

extra_data_ce = Signal()
extra_data_last = Signal()
36 changes: 29 additions & 7 deletions artiq/test/gateware/drtio/test_full_stack.py
Original file line number Diff line number Diff line change
@@ -1,10 +1,12 @@
import unittest
from types import SimpleNamespace
import random

from migen import *

from artiq.gateware.drtio import *
from artiq.gateware import rtio
from artiq.gateware.rtio import rtlink
from artiq.gateware.rtio.phy import ttl_simple
from artiq.coredevice.exceptions import *

@@ -19,13 +21,11 @@ def __init__(self, nwords):
self.alice = SimpleNamespace(
encoder=SimpleNamespace(k=a2b_k, d=a2b_d),
decoders=[SimpleNamespace(k=k, d=d) for k, d in zip(b2a_k, b2a_d)],
rx_reset=Signal(),
rx_ready=1
)
self.bob = SimpleNamespace(
encoder=SimpleNamespace(k=b2a_k, d=b2a_d),
decoders=[SimpleNamespace(k=k, d=d) for k, d in zip(a2b_k, a2b_d)],
rx_reset=Signal(),
rx_ready=1
)

@@ -35,6 +35,14 @@ def resync(self, signal):
return signal


class LargeDataReceiver(Module):
def __init__(self, width):
self.rtlink = rtlink.Interface(rtlink.OInterface(width))
self.received_data = Signal(width)
self.sync.rio_phy += If(self.rtlink.o.stb,
self.received_data.eq(self.rtlink.o.data))


class DUT(Module):
def __init__(self, nwords):
self.ttl0 = Signal()
@@ -47,9 +55,11 @@ def __init__(self, nwords):
rx_synchronizer = DummyRXSynchronizer()
self.submodules.phy0 = ttl_simple.Output(self.ttl0)
self.submodules.phy1 = ttl_simple.Output(self.ttl1)
self.submodules.phy2 = LargeDataReceiver(512)
rtio_channels = [
rtio.Channel.from_phy(self.phy0, ofifo_depth=4),
rtio.Channel.from_phy(self.phy1, ofifo_depth=4)
rtio.Channel.from_phy(self.phy1, ofifo_depth=4),
rtio.Channel.from_phy(self.phy2, ofifo_depth=4),
]
self.submodules.satellite = DRTIOSatellite(
self.transceivers.bob, rx_synchronizer, rtio_channels)
@@ -66,11 +76,13 @@ def test_controller(self):

ttl_changes = []
correct_ttl_changes = [
# from test_pulses
(203, 0),
(208, 0),
(208, 1),
(214, 1),

# from test_fifo_space
(414, 0),
(454, 0),
(494, 0),
@@ -138,6 +150,15 @@ def test_sequence_error():
yield from write(0, 1)
delay(200*8)

def test_large_data():
correct_large_data = random.Random(0).randrange(2**512-1)
self.assertNotEqual((yield dut.phy2.received_data), correct_large_data)
delay(10*8)
yield from write(2, correct_large_data)
for i in range(40):
yield
self.assertEqual((yield dut.phy2.received_data), correct_large_data)

def test_fifo_space():
delay(200*8)
max_wlen = 0
@@ -163,11 +184,11 @@ def test_fifo_emptied():
def test_tsc_error():
err_present = yield from mgr.packet_err_present.read()
self.assertEqual(err_present, 0)
yield from csrs.tsc_correction.write(10000000)
yield from csrs.tsc_correction.write(100000000)
yield from csrs.set_time.write(1)
for i in range(5):
for i in range(15):
yield
delay(10000)
delay(10000*8)
yield from write(0, 1)
for i in range(10):
yield
@@ -189,6 +210,7 @@ def test():
yield from test_pulses()
yield from test_sequence_error()
yield from test_fifo_space()
yield from test_large_data()
yield from test_fifo_emptied()
yield from test_tsc_error()

@@ -205,7 +227,7 @@ def check_ttls():
yield
cycle += 1

run_simulation(dut,
run_simulation(dut,
{"sys": test(), "rtio": check_ttls()}, self.clocks)
self.assertEqual(ttl_changes, correct_ttl_changes)