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sbourdeauducqsbourdeauducq
committedDec 3, 2016
drtio: add false paths between sys and transceiver clocks
·
8.03.0
1 parent 4b97b9f commit 5d145ff

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3 files changed

+26
-16
lines changed

3 files changed

+26
-16
lines changed
 

Diff for: ‎artiq/gateware/drtio/transceiver/gtx_7series.py

+11-12
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,8 @@ class GTX_20X(Module):
1111
# The transceiver clock on clock_pads must be at the RTIO clock
1212
# frequency when clock_div2=False, and 2x that frequency when
1313
# clock_div2=True.
14-
def __init__(self, platform,
15-
clock_pads, tx_pads, rx_pads,
16-
sys_clk_freq, clock_div2=False):
14+
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
15+
clock_div2=False):
1716
self.submodules.encoder = ClockDomainsRenamer("rtio")(
1817
Encoder(2, True))
1918
self.decoders = [ClockDomainsRenamer("rtio_rx")(
@@ -22,6 +21,11 @@ def __init__(self, platform,
2221

2322
self.rx_ready = Signal()
2423

24+
# transceiver direct clock outputs
25+
# useful to specify clock constraints in a way palatable to Vivado
26+
self.txoutclk = Signal()
27+
self.rxoutclk = Signal()
28+
2529
# # #
2630

2731
refclk = Signal()
@@ -50,9 +54,7 @@ def __init__(self, platform,
5054
self.comb += tx_init.cplllock.eq(cplllock), \
5155
rx_init.cplllock.eq(cplllock)
5256

53-
txoutclk = Signal()
5457
txdata = Signal(20)
55-
rxoutclk = Signal()
5658
rxdata = Signal(20)
5759
self.specials += \
5860
Instance("GTXE2_CHANNEL",
@@ -88,7 +90,7 @@ def __init__(self, platform,
8890
# TX clock
8991
p_TXBUF_EN="FALSE",
9092
p_TX_XCLK_SEL="TXUSR",
91-
o_TXOUTCLK=txoutclk,
93+
o_TXOUTCLK=self.txoutclk,
9294
i_TXSYSCLKSEL=0b00,
9395
i_TXOUTCLKSEL=0b11,
9496

@@ -134,7 +136,7 @@ def __init__(self, platform,
134136
i_RXDDIEN=1,
135137
i_RXSYSCLKSEL=0b00,
136138
i_RXOUTCLKSEL=0b010,
137-
o_RXOUTCLK=rxoutclk,
139+
o_RXOUTCLK=self.rxoutclk,
138140
i_RXUSRCLK=ClockSignal("rtio_rx"),
139141
i_RXUSRCLK2=ClockSignal("rtio_rx"),
140142
p_RXCDR_CFG=0x03000023FF10100020,
@@ -165,20 +167,17 @@ def __init__(self, platform,
165167
self.sync += tx_reset_deglitched.eq(~tx_init.done)
166168
self.clock_domains.cd_rtio = ClockDomain()
167169
self.specials += [
168-
Instance("BUFG", i_I=txoutclk, o_O=self.cd_rtio.clk),
170+
Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio.clk),
169171
AsyncResetSynchronizer(self.cd_rtio, tx_reset_deglitched)
170172
]
171173
rx_reset_deglitched = Signal()
172174
rx_reset_deglitched.attr.add("no_retiming")
173175
self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
174176
self.clock_domains.cd_rtio_rx = ClockDomain()
175177
self.specials += [
176-
Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk),
178+
Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx.clk),
177179
AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
178180
]
179-
platform.add_period_constraint(txoutclk, 1e9/self.rtio_clk_freq)
180-
platform.add_period_constraint(rxoutclk, 1e9/self.rtio_clk_freq)
181-
platform.add_false_path_constraints(txoutclk, rxoutclk)
182181

183182
self.comb += [
184183
txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])),

Diff for: ‎artiq/gateware/targets/kc705_drtio_master.py

+7-2
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ def __init__(self, cfg, medium, **kwargs):
5959
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
6060
# simple TTLs
6161
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
62-
platform=platform,
6362
clock_pads=platform.request("sgmii_clock"),
6463
tx_pads=tx_pads,
6564
rx_pads=rx_pads,
@@ -70,7 +69,6 @@ def __init__(self, cfg, medium, **kwargs):
7069
# with SAWG on local RTIO and AD9154-FMC-EBZ
7170
platform.register_extension(fmc_clock_io)
7271
self.submodules.transceiver = gtx_7series.GTX_3G(
73-
platform=platform,
7472
clock_pads=platform.request("ad9154_refclk"),
7573
tx_pads=tx_pads,
7674
rx_pads=rx_pads,
@@ -80,6 +78,13 @@ def __init__(self, cfg, medium, **kwargs):
8078
self.submodules.drtio = DRTIOMaster(self.transceiver)
8179
self.csr_devices.append("drtio")
8280

81+
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
82+
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
83+
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
84+
platform.add_false_path_constraints(
85+
self.crg.cd_sys.clk,
86+
self.transceiver.txoutclk, self.transceiver.rxoutclk)
87+
8388
rtio_channels = []
8489
for i in range(8):
8590
phy = ttl_simple.Output(platform.request("user_led", i))

Diff for: ‎artiq/gateware/targets/kc705_drtio_satellite.py

+8-2
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,6 @@ def __init__(self, cfg, medium, toolchain):
165165
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
166166
# simple TTLs
167167
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
168-
platform=platform,
169168
clock_pads=platform.request("sgmii_clock"),
170169
tx_pads=tx_pads,
171170
rx_pads=rx_pads,
@@ -176,7 +175,6 @@ def __init__(self, cfg, medium, toolchain):
176175
# with SAWG on local RTIO and AD9154-FMC-EBZ
177176
platform.register_extension(fmc_clock_io)
178177
self.submodules.transceiver = gtx_7series.GTX_3G(
179-
platform=platform,
180178
clock_pads=platform.request("ad9154_refclk"),
181179
tx_pads=tx_pads,
182180
rx_pads=rx_pads,
@@ -188,6 +186,14 @@ def __init__(self, cfg, medium, toolchain):
188186
self.submodules.drtio = DRTIOSatellite(
189187
self.transceiver, self.rx_synchronizer, rtio_channels)
190188

189+
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
190+
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
191+
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
192+
platform.add_false_path_constraints(
193+
sys_clock_pads,
194+
self.transceiver.txoutclk, self.transceiver.rxoutclk)
195+
196+
191197
def build(self, *args, **kwargs):
192198
self.platform.build(self, *args, **kwargs)
193199

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