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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: f6071a58125a
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 8, 2016

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    b7a308d View commit details
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    f6071a5 View commit details
Showing with 17 additions and 10 deletions.
  1. +15 −8 artiq/gateware/dsp/fir.py
  2. +2 −2 artiq/gateware/dsp/sawg.py
23 changes: 15 additions & 8 deletions artiq/gateware/dsp/fir.py
Original file line number Diff line number Diff line change
@@ -47,26 +47,30 @@ def __init__(self, coefficients, width=16, shift=None):
self.i = Signal((width, True))
self.o = Signal((width, True))
n = len(coefficients)
self.latency = (n + 1)//2 + 1
self.latency = (n + 1)//2 + 2

###

# Delay line: increasing delay
x = [Signal((width, True)) for _ in range(n)]
self.sync += [xi.eq(xj) for xi, xj in zip(x, [self.i] + x)]

# Wire up output
if shift is None:
shift = width - 1

# Make products
o = []
for i, c in enumerate(coefficients):
# simplify for halfband and symmetric filters
if c == 0 or c in coefficients[i + 1:]:
continue
o.append(c*reduce(add, [
m = Signal((width + shift, True))
self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[::-1], coefficients) if cj == c
]))
o.append(m)

if shift is None:
shift = width - 1
# Make sum
self.sync += self.o.eq(reduce(add, o) >> shift)


@@ -85,7 +89,7 @@ def __init__(self, coefficients, parallelism, width=16, shift=None):
# input and output: old to young, decreasing delay
self.i = [Signal((width, True)) for i in range(p)]
self.o = [Signal((width, True)) for i in range(p)]
self.latency = (n + 1)//2//parallelism + 2 # minus .5
self.latency = (n + 1)//2//parallelism + 3 # minus one sample

###

@@ -96,16 +100,19 @@ def __init__(self, coefficients, parallelism, width=16, shift=None):
if shift is None:
shift = width - 1

# wire up each output
for j in range(p):
# Make products
o = []
for i, c in enumerate(coefficients):
# simplify for halfband and symmetric filters
if c == 0 or c in coefficients[i + 1:]:
continue
o.append(c*reduce(add, [
m = Signal((width + shift, True))
self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
]))
o.append(m)
# Make sum
self.sync += self.o[j].eq(reduce(add, o) >> shift)


4 changes: 2 additions & 2 deletions artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -177,6 +177,8 @@ def __init__(self, width=16, parallelism=4, widths=None, orders=None):
b.ce.eq(cfg.ce),
u.o.ack.eq(cfg.ce),
Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
b.i.x.eq(hbf[0].o[0]), # FIXME: rip up
b.i.y.eq(hbf[1].o[0]),
]
self.sync += [
hbf[0].i.eq(self.sat_add(a1.xo[0], a2.xo[0],
@@ -185,8 +187,6 @@ def __init__(self, width=16, parallelism=4, widths=None, orders=None):
hbf[1].i.eq(self.sat_add(a1.yo[0], a2.yo[0],
limits=cfg.limits[1],
clipped=cfg.clipped[1])),
b.i.x.eq(hbf[0].o[0]), # FIXME: rip up
b.i.y.eq(hbf[1].o[0]),
eqh(du.i, u.o.a0),
]
# wire up outputs and q_{i,o} exchange