m-labs · Dec 13, 2016 · Dec 13, 2016
diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py
@@ -74,14 +74,14 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
         local_reset = Signal(reset=1)
         self.sync += local_reset.eq(self.csrs.reset.re)
         local_reset.attr.add("no_retiming")
-        self.clock_domains.cd_rsys = ClockDomain()
-        self.clock_domains.cd_rio = ClockDomain()
+        self.clock_domains.cd_sys_with_rst = ClockDomain()
+        self.clock_domains.cd_rtio_with_rst = ClockDomain()
         self.comb += [
-            self.cd_rsys.clk.eq(ClockSignal()),
-            self.cd_rsys.rst.eq(local_reset)
+            self.cd_sys_with_rst.clk.eq(ClockSignal()),
+            self.cd_sys_with_rst.rst.eq(local_reset)
         ]
-        self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
-        self.specials += AsyncResetSynchronizer(self.cd_rio, local_reset)
+        self.comb += self.cd_rtio_with_rst.clk.eq(ClockSignal("rtio"))
+        self.specials += AsyncResetSynchronizer(self.cd_rtio_with_rst, local_reset)
 
         # remote channel status cache
         fifo_spaces_mem = Memory(16, channel_count)
@@ -107,7 +107,7 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
             )
         ]
 
-        fsm = ClockDomainsRenamer("rsys")(FSM())
+        fsm = ClockDomainsRenamer("sys_with_rst")(FSM())
         self.submodules += fsm
 
         status_wait = Signal()
@@ -120,15 +120,15 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
         ]
         sequence_error_set = Signal()
         underflow_set = Signal()
-        self.sync.rio += [
+        self.sync.sys_with_rst += [
             If(self.cri.cmd == cri.commands["o_underflow_reset"], status_underflow.eq(0)),
             If(self.cri.cmd == cri.commands["o_sequence_error_reset"], status_sequence_error.eq(0)),
             If(underflow_set, status_underflow.eq(1)),
             If(sequence_error_set, status_sequence_error.eq(1))
         ]
 
         signal_fifo_space_timeout = Signal()
-        self.sync += [
+        self.sync.sys_with_rst += [
             If(self.csrs.o_fifo_space_timeout.re, self.csrs.o_fifo_space_timeout.w.eq(0)),
             If(signal_fifo_space_timeout, self.csrs.o_fifo_space_timeout.w.eq(1))
         ]

diff --git a/artiq/gateware/drtio/rt_packets.py b/artiq/gateware/drtio/rt_packets.py
@@ -487,7 +487,7 @@ def __init__(self, link_layer, write_fifo_depth=4):
         self.submodules += rx_dp
 
         # Write FIFO and extra data count
-        wfifo = ClockDomainsRenamer({"write": "rsys", "read": "rio"})(
+        wfifo = ClockDomainsRenamer({"write": "sys_with_rst", "read": "rtio_with_rst"})(
             AsyncFIFO(64+16+16+512, write_fifo_depth))
         self.submodules += wfifo
         write_timestamp_d = Signal(64)

diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
@@ -9,6 +9,7 @@
 from misoc.integration.soc_core import mem_decoder
 from misoc.integration.builder import builder_args, builder_argdict
 
+from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
 from artiq.gateware.soc import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple
@@ -17,14 +18,6 @@
 from artiq import __version__ as artiq_version
 
 
-fmc_clock_io = [
-    ("ad9154_refclk", 0,
-        Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
-        Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
-    )
-]
-
-
 class Master(MiniSoC, AMPSoC):
     mem_map = {
         "timer_kernel":  0x10000000,
@@ -69,7 +62,7 @@ def __init__(self, cfg, medium, **kwargs):
         elif cfg == "sawg_3g":
             # 3Gb link, 150MHz RTIO clock
             # with SAWG on local RTIO and AD9154-FMC-EBZ
-            platform.register_extension(fmc_clock_io)
+            platform.register_extension(ad9154_fmc_ebz)
             self.submodules.transceiver = gtx_7series.GTX_3G(
                 clock_pads=platform.request("ad9154_refclk"),
                 tx_pads=tx_pads,

diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py
@@ -8,6 +8,7 @@
 from misoc.integration.soc_core import mem_decoder
 from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
 
+from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple
 from artiq.gateware.drtio.transceiver import gtx_7series
@@ -116,14 +117,6 @@ def __init__(self, platform, sys_clk_freq):
             )
 
 
-fmc_clock_io = [
-    ("ad9154_refclk", 0,
-        Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
-        Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
-    )
-]
-
-
 class Satellite(BaseSoC):
     mem_map = {
         "drtio_aux": 0x50000000,
@@ -181,7 +174,7 @@ def __init__(self, cfg, medium, **kwargs):
         elif cfg == "sawg_3g":
             # 3Gb link, 150MHz RTIO clock
             # with SAWG on local RTIO and AD9154-FMC-EBZ
-            platform.register_extension(fmc_clock_io)
+            platform.register_extension(ad9154_fmc_ebz)
             self.submodules.transceiver = gtx_7series.GTX_3G(
                 clock_pads=platform.request("ad9154_refclk"),
                 tx_pads=tx_pads,

diff --git a/artiq/test/gateware/drtio/test_full_stack.py b/artiq/test/gateware/drtio/test_full_stack.py
@@ -67,7 +67,8 @@ def __init__(self, nwords):
 
 class TestFullStack(unittest.TestCase):
     clocks = {"sys": 8, "rtio": 5, "rtio_rx": 5,
-              "rsys": 8, "rio": 5, "rio_phy": 5}
+              "rio": 5, "rio_phy": 5,
+              "sys_with_rst": 8, "rtio_with_rst": 5}
 
     def test_controller(self):
         dut = DUT(2)