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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: cfb66117af89
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 20, 2016

  1. fir: cleanup halfgen4

    @jordens
    jordens committed Dec 20, 2016
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    f310274 View commit details

  2. fir: size hint for pre-adder

    @jordens
    jordens committed Dec 20, 2016
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    cfb6611 View commit details
Showing with 18 additions and 8 deletions.
  1. +18 −8 artiq/gateware/dsp/fir.py
26 changes: 18 additions & 8 deletions artiq/gateware/dsp/fir.py
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,10 @@
from operator import add
from functools import reduce
from collections import namedtuple
import numpy as np
from migen import *


def halfgen4(width, n):
def halfgen4(width, n, df=1e-3):
"""
http://recycle.lbl.gov/~ldoolitt/halfband
@@ -24,13 +23,18 @@ def halfgen4(width, n):

target = .5*np.ones_like(wfit)
basis = np.cos(wfit*np.arange(1, 2*n, 2))
l = np.linalg.pinv(basis)@target

weight = np.ones_like(wfit)

f0 = None

for i in range(40):
err = np.fabs(basis@l - .5)
weight[err > .99*np.max(err)] *= 1 + 1.5/(i + 11)
l = np.linalg.pinv(basis*weight)@(target*weight)
err = np.fabs(basis@l - .5)
f = np.max(err)/np.mean(err)
if f0 and (f0 - f)/(f0 + f) < df/2:
break
f0 = f
weight[err > (1 - df)*np.max(err)] *= 1 + 1.5/(i + 11)
a = np.c_[l, np.zeros_like(l)].ravel()[:-1]
a = np.r_[a[::-1], 1, a]/2
return a
@@ -79,7 +83,10 @@ def __init__(self, coefficients, width=16, shift=None):
else:
self.comb += o0.eq(o + m)
assert js[0] - delay >= 0
self.sync += m.eq(c*reduce(add, [x[j - delay] for j in js]))
xs = [x[j - delay] for j in js]
s = Signal((bits_for(len(xs)) - 1 + len(xs[0]), True))
self.comb += s.eq(sum(xs))
self.sync += m.eq(c*s)
# symmetric rounding
if shift:
self.comb += o.eq((1 << shift - 1) - 1)
@@ -132,7 +139,10 @@ def __init__(self, coefficients, parallelism, width=16, shift=None):
else:
self.comb += o0.eq(o + m)
assert js[0] - delay >= 0
self.sync += m.eq(c*reduce(add, [x[j - delay] for j in js]))
xs = [x[j - delay] for j in js]
s = Signal((bits_for(len(xs)) - 1 + len(xs[0]), True))
self.comb += s.eq(sum(xs))
self.sync += m.eq(c*s)
# symmetric rounding
if shift:
self.comb += o.eq((1 << shift - 1) - 1)