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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: c419c422fa9e
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  • 2 commits
  • 6 files changed
  • 1 contributor

Commits on Nov 28, 2016

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61 changes: 61 additions & 0 deletions artiq/examples/drtio/device_db.pyon
Original file line number Diff line number Diff line change
@@ -83,5 +83,66 @@
"arguments": {"channel": 9}
},

"led0": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010000},
},
"led1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010001},
},
"led2": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010002},
},
"led3": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010003},
},
"led4": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010004},
},
"led5": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010005},
},
"led6": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010006},
},
"led7": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010007},
},

"smap": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010008}
},
"sman": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010009}
},

}
13 changes: 10 additions & 3 deletions artiq/examples/drtio/repository/blink_forever.py
Original file line number Diff line number Diff line change
@@ -4,17 +4,24 @@
class BlinkForever(EnvExperiment):
def build(self):
self.setattr_device("core")
self.leds = [self.get_device("rled" + str(i)) for i in range(8)]
self.rleds = [self.get_device("rled" + str(i)) for i in range(8)]
self.leds = [self.get_device("led" + str(i)) for i in range(8)]

@kernel
def run(self):
self.core.reset()

while True:
for led in self.leds:
led.pulse(250*ms)
with parallel:
for led in self.leds:
led.pulse(250*ms)
for led in self.rleds:
led.pulse(250*ms)
t = now_mu()
for led in self.leds:
at_mu(t)
led.pulse(500*ms)
for led in self.rleds:
at_mu(t)
led.pulse(500*ms)
delay(250*ms)
2 changes: 1 addition & 1 deletion artiq/gateware/rtio/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
from artiq.gateware.rtio.cri import KernelInitiator
from artiq.gateware.rtio.cri import KernelInitiator, CRIDecoder
from artiq.gateware.rtio.core import Channel, LogChannel, Core
from artiq.gateware.rtio.analyzer import Analyzer
from artiq.gateware.rtio.moninj import MonInj
31 changes: 31 additions & 0 deletions artiq/gateware/rtio/cri.py
Original file line number Diff line number Diff line change
@@ -116,3 +116,34 @@ def __init__(self, cri=None):
self.o_data.we.eq(self.o_timestamp.re),
]
self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))


class CRIDecoder(Module):
def __init__(self, slaves=2, master=None):
if isinstance(slaves, int):
slaves = [Interface() for _ in range(slaves)]
if master is None:
master = Interface()
self.slaves = slaves
self.master = master

# # #

selected = Signal(8)
self.sync += selected.eq(self.master.chan_sel[16:])

# master -> slave
for n, slave in enumerate(slaves):
for name, size, direction in _layout:
if direction == DIR_M_TO_S and name != "cmd":
self.comb += getattr(slave, name).eq(getattr(master, name))
self.comb += If(selected == n, slave.cmd.eq(master.cmd))

# slave -> master
cases = dict()
for n, slave in enumerate(slaves):
cases[n] = []
for name, size, direction in _layout:
if direction == DIR_S_TO_M:
cases[n].append(getattr(master, name).eq(getattr(slave, name)))
self.comb += Case(selected, cases)
18 changes: 16 additions & 2 deletions artiq/gateware/targets/kc705_drtio_master.py
Original file line number Diff line number Diff line change
@@ -9,6 +9,7 @@

from artiq.gateware.soc import AMPSoC, build_artiq_soc
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import gtx_7series
from artiq.gateware.drtio import DRTIOMaster
from artiq import __version__ as artiq_version
@@ -42,10 +43,23 @@ def __init__(self, **kwargs):
sys_clk_freq=self.clk_freq,
clock_div2=True)
self.submodules.drtio = DRTIOMaster(self.transceiver)
self.submodules.rtio = rtio.KernelInitiator(self.drtio.cri)
self.register_kernel_cpu_csrdevice("rtio")
self.csr_devices.append("drtio")

rtio_channels = []
for i in range(8):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
phy = ttl_simple.Inout(platform.request(sma))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_core = rtio.Core(rtio_channels)

self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
self.submodules.rtio = rtio.KernelInitiator(self.cridec.cri)
self.register_kernel_cpu_csrdevice("rtio")


def main():
parser = argparse.ArgumentParser(
4 changes: 2 additions & 2 deletions artiq/runtime.rs/src/drtio.rs
Original file line number Diff line number Diff line change
@@ -21,7 +21,7 @@ fn drtio_init_channel(channel: u16) {

csr::drtio::o_reset_channel_status_write(1);
csr::drtio::o_get_fifo_space_write(1);
while csr::drtio::o_wait_read() == 1 {} // TODO: timeout
while csr::drtio::o_wait_read() == 1 {}
info!("FIFO space on channel {} is {}", channel, csr::drtio::o_dbg_fifo_space_read());

csr::drtio::chan_sel_override_en_write(0);
@@ -33,7 +33,7 @@ pub fn link_thread(waiter: Waiter, _spawner: Spawner) {
waiter.until(drtio_link_is_up).unwrap();
info!("link RX is up");

waiter.sleep(500).unwrap();
waiter.sleep(600).unwrap();
info!("wait for remote side done");

drtio_sync_tsc();