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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 4669d3f02f9f
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 6, 2016

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    f4b7d39 View commit details
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    4669d3f View commit details
Showing with 43 additions and 29 deletions.
  1. +5 −0 artiq/gateware/targets/kc705_drtio_master.py
  2. +38 −29 artiq/gateware/targets/kc705_drtio_satellite.py
5 changes: 5 additions & 0 deletions artiq/gateware/targets/kc705_drtio_master.py
Original file line number Diff line number Diff line change
@@ -6,6 +6,7 @@
from migen.build.generic_platform import *

from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
from misoc.integration.soc_core import mem_decoder
from misoc.integration.builder import builder_args, builder_argdict

from artiq.gateware.soc import AMPSoC, build_artiq_soc
@@ -29,6 +30,7 @@ class Master(MiniSoC, AMPSoC):
"timer_kernel": 0x10000000,
"rtio": 0x20000000,
"rtio_dma": 0x30000000,
"drtio_aux": 0x60000000,
"mailbox": 0x70000000
}
mem_map.update(MiniSoC.mem_map)
@@ -77,6 +79,9 @@ def __init__(self, cfg, medium, **kwargs):
raise ValueError
self.submodules.drtio = DRTIOMaster(self.transceiver)
self.csr_devices.append("drtio")
self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
self.drtio.aux_controller.bus)
self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)

rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
67 changes: 38 additions & 29 deletions artiq/gateware/targets/kc705_drtio_satellite.py
Original file line number Diff line number Diff line change
@@ -2,18 +2,21 @@

from migen import *
from migen.build.generic_platform import *
from migen.build.platforms import kc705

from misoc.cores.i2c import *
from misoc.cores.sequencer import *
from misoc.integration.builder import *
from misoc.integration.soc_core import mem_decoder
from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict

from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import gtx_7series
from artiq.gateware.drtio import DRTIOSatellite
from artiq import __version__ as artiq_version


# TODO: parameters for sawg_3g
# TODO: move I2C programming to softcore CPU
def get_i2c_program(sys_clk_freq):
# NOTE: the logical parameters DO NOT MAP to physical values written
# into registers. They have to be mapped; see the datasheet.
@@ -121,9 +124,21 @@ def __init__(self, platform, sys_clk_freq):
]


class Satellite(Module):
def __init__(self, cfg, medium, toolchain):
self.platform = platform = kc705.Platform(toolchain=toolchain)
class Satellite(BaseSoC):
mem_map = {
"drtio_aux": 0x60000000,
}
mem_map.update(BaseSoC.mem_map)

def __init__(self, cfg, medium, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
**kwargs)

platform = self.platform

rtio_channels = []
for i in range(8):
@@ -135,16 +150,9 @@ def __init__(self, cfg, medium, toolchain):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))

sys_clock_pads = platform.request("clk156")
self.clock_domains.cd_sys = ClockDomain(reset_less=True)
self.specials += Instance("IBUFGDS",
i_I=sys_clock_pads.p, i_IB=sys_clock_pads.n,
o_O=self.cd_sys.clk)
sys_clk_freq = 156000000

i2c_master = I2CMaster(platform.request("i2c"))
sequencer = ResetInserter()(Sequencer(get_i2c_program(sys_clk_freq)))
si5324_reset_clock = Si5324ResetClock(platform, sys_clk_freq)
sequencer = ResetInserter()(Sequencer(get_i2c_program(self.clk_freq)))
si5324_reset_clock = Si5324ResetClock(platform, self.clk_freq)
self.submodules += i2c_master, sequencer, si5324_reset_clock
self.comb += [
sequencer.bus.connect(i2c_master.bus),
@@ -168,7 +176,7 @@ def __init__(self, cfg, medium, toolchain):
clock_pads=platform.request("sgmii_clock"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=sys_clk_freq,
sys_clk_freq=self.clk_freq,
clock_div2=True)
elif cfg == "sawg_3g":
# 3Gb link, 150MHz RTIO clock
@@ -178,33 +186,32 @@ def __init__(self, cfg, medium, toolchain):
clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=sys_clk_freq)
sys_clk_freq=self.clk_freq)
else:
raise ValueError
self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
self.transceiver.rtio_clk_freq)
self.submodules.drtio = DRTIOSatellite(
self.transceiver, self.rx_synchronizer, rtio_channels)
self.csr_devices.append("rx_synchronizer")
self.csr_devices.append("drtio")
self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
self.drtio.aux_controller.bus)
self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)

rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
sys_clock_pads,
platform.lookup_request("clk200"),
self.transceiver.txoutclk, self.transceiver.rxoutclk)


def build(self, *args, **kwargs):
self.platform.build(self, *args, **kwargs)


def main():
parser = argparse.ArgumentParser(description="KC705 DRTIO satellite")
parser.add_argument("--toolchain", default="vivado",
help="FPGA toolchain to use: ise, vivado")
parser.add_argument("--output-dir", default="drtiosat_kc705",
help="output directory for generated "
"source files and binaries")
parser = argparse.ArgumentParser(
description="ARTIQ with DRTIO on KC705 - Satellite")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-c", "--config", default="simple_gbe",
help="configuration: simple_gbe/sawg_3g "
"(default: %(default)s)")
@@ -213,8 +220,10 @@ def main():
"(default: %(default)s)")
args = parser.parse_args()

top = Satellite(args.config, args.medium, args.toolchain)
top.build(build_dir=args.output_dir)
soc = Satellite(args.config, args.medium, **soc_kc705_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()


if __name__ == "__main__":
main()