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1 parent c413d95 commit f3c50a3Copy full SHA for f3c50a3
artiq/gateware/rtio/dma.py
@@ -350,12 +350,12 @@ def __init__(self, membus):
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self.submodules += fsm
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fsm.act("IDLE",
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- If(self.enable.re & self.enable.r, NextState("FLOWING"))
+ If(self.enable.re, NextState("FLOWING"))
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)
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fsm.act("FLOWING",
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self.enable.w.eq(1),
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flow_enable.eq(1),
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- If(self.slicer.end_marker_found | (self.enable.re & ~self.enable.r),
+ If(self.slicer.end_marker_found,
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NextState("FLUSH")
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