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rtio: always read full DMA sequence
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sbourdeauducq committed Dec 5, 2016
1 parent c413d95 commit f3c50a3
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions artiq/gateware/rtio/dma.py
Original file line number Diff line number Diff line change
@@ -350,12 +350,12 @@ def __init__(self, membus):
self.submodules += fsm

fsm.act("IDLE",
If(self.enable.re & self.enable.r, NextState("FLOWING"))
If(self.enable.re, NextState("FLOWING"))
)
fsm.act("FLOWING",
self.enable.w.eq(1),
flow_enable.eq(1),
If(self.slicer.end_marker_found | (self.enable.re & ~self.enable.r),
If(self.slicer.end_marker_found,
NextState("FLUSH")
)
)

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