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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 598da09a93a0
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 8, 2016

  1. test/sawg: patch spline

    jordens committed Dec 8, 2016
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    efc9504 View commit details
  2. Copy the full SHA
    f4ceace View commit details
  3. sawg: fix latency

    jordens committed Dec 8, 2016
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    598da09 View commit details
Showing with 4 additions and 4 deletions.
  1. +1 −1 artiq/gateware/dsp/sawg.py
  2. 0 artiq/test/gateware/{test_fir.py → fir.py}
  3. +3 −3 artiq/test/gateware/test_sawg_fe.py
2 changes: 1 addition & 1 deletion artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -166,7 +166,7 @@ def __init__(self, width=16, parallelism=4, widths=None, orders=None):
self.widths = widths
self.orders = orders
self.parallelism = parallelism
self.latency = a1.latency + b.latency + 2
self.latency = a1.latency + hbf[0].latency + b.latency + 2
self.cordic_gain = a1.gain*b.gain

###
File renamed without changes.
6 changes: 3 additions & 3 deletions artiq/test/gateware/test_sawg_fe.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
import migen as mg
from numpy import int32

from artiq.coredevice import sawg
from artiq.coredevice import sawg, spline
from artiq.language import (at_mu, now_mu, delay,
core as core_language)
from artiq.gateware.rtio.phy.sawg import Channel
@@ -36,7 +36,7 @@ class SAWGTest(unittest.TestCase):
def setUp(self):
core_language.set_time_manager(sim_time.Manager())
self.rtio_manager = RTIOManager()
self.rtio_manager.patch(sawg)
self.rtio_manager.patch(spline)
self.core = sim_devices.Core({})
self.core.coarse_ref_period = 6.66666
self.t = self.core.coarse_ref_period
@@ -46,7 +46,7 @@ def setUp(self):
parallelism=self.channel.parallelism)

def tearDown(self):
self.rtio_manager.unpatch(sawg)
self.rtio_manager.unpatch(spline)

def test_instantiate(self):
pass