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sawg: reduce coefficient width
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jordens committed Dec 8, 2016
1 parent 598da09 commit 18e3f58
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -146,9 +146,9 @@ def __init__(self, width=16, parallelism=4, widths=None, orders=None):

self.submodules.a1 = a1 = SplineParallelDDS(widths, orders)
self.submodules.a2 = a2 = SplineParallelDDS(widths, orders)
coeff = [[int(round((1 << 26) * ci)) for ci in c]
coeff = [[int(round((1 << 18)*ci)) for ci in c]
for c in halfgen4_cascade(parallelism, width=.4, order=8)]
hbf = [ParallelHBFUpsampler(coeff, width=width, shift=25)
hbf = [ParallelHBFUpsampler(coeff, width=width, shift=17)
for i in range(2)]
self.submodules.b = b = SplineParallelDUC(
widths._replace(a=len(a1.xo[0]), f=widths.f - width), orders,

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