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drtio: fix aux controller clock domain mistakes
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sbourdeauducq committed Dec 14, 2016
1 parent 527757b commit e959210
Showing 1 changed file with 4 additions and 2 deletions.
6 changes: 4 additions & 2 deletions artiq/gateware/drtio/aux_controller.py
Original file line number Diff line number Diff line change
@@ -20,7 +20,8 @@ def __init__(self, link_layer, min_mem_dw):
self.aux_tx = CSR()
self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))

converter = stream.Converter(mem_dw, ll_dw)
converter = ClockDomainsRenamer("rtio")(
stream.Converter(mem_dw, ll_dw))
self.submodules += converter

# when continuously fed, the Converter outputs data continuously
@@ -107,7 +108,8 @@ def __init__(self, link_layer, min_mem_dw):
mem_dw = max(min_mem_dw, ll_dw)
self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))

converter = stream.Converter(ll_dw, mem_dw)
converter = ClockDomainsRenamer("rtio_rx")(
stream.Converter(ll_dw, mem_dw))
self.submodules += converter

# when continuously drained, the Converter accepts data continuously

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