Commits on Oct 2, 2018

1. Updating submodules. …

    * litedram changed from ea1ac4d to 5b02791
       * 5b02791 - modules: add tCCD to all modules <Florent Kermarrec>
       * 6c7a804 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell>
       *   208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
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       | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec>
       | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec>
       | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec>
       | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec>
       | * 1bc016c - test: add test_examples <Florent Kermarrec>
       | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec>
       | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec>
       * | 69eaf84 - Fix DDR2 and below compilation failure <>
       |/
       *   70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
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       | * 5820970 - frontend/crossbar: fix #49 <Florent Kermarrec>
       * | 71f78d9 - Fix reordering controller rejecting all commands <>
       * | 8f14211 - Account for CWL in write to read timing <>
       |/
       * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
       *   06ca53d - Merge pull request #48 from enjoy-digital/staging <enjoy-digital>
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       | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
       | |\
       | |/
       |/|
       * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
       * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
       * |   869c8ee - Merge pull request #46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
       |\ \
       | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
       * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
       |/ /
       * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
       * |   42ccf05 - Merge pull request #45 from enjoy-digital/tRAS_FIX <enjoy-digital>
       |\ \
       | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
       | * | 177d739 - Implement tRAS <John Sully>
       * | |   5902027 - Merge pull request #44 from enjoy-digital/tRC_Fix <enjoy-digital>
       |\ \ \
       | |/ /
       | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
       |/ /
       * |   1777720 - Merge pull request #42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
       |\ \
       | * | 06c8c2a - The actual fix <John Sully>
       | * | e22580f - remove unnecessary file <John Sully>
       | * | c028786 - Fix overflow bug from code review <John Sully>
       | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
       |/ /
       | *   04aa04d - Merge pull request #43 from enjoy-digital/EfficencyFixes <enjoy-digital>
       | |\
       |/ /
       | * c4bd842 - Fix many bugs <John Sully>
       | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
       |/
       * c12404e - README: Add ECC <Florent Kermarrec>
       * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
       * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>
   
    * liteeth changed from 3d86844 to 40b99ec
       * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
       * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>
   
    * litepcie changed from 3e8de2d to a09d225
       * a09d225 - test: use new RemoteClient import <Florent Kermarrec>
   
    * litesata changed from fb72044 to b78a731
       * b78a731 - test: use new RemoteClient import <Florent Kermarrec>
   
    * litescope changed from 686db4f to 1634fa3
       * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
       * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>
   
    * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b
       * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski>
       * 56f359d - Added icebreaker platform. (#135) <Piotr Esden-Tempski>
       * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (#134) <hartytp>
       * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
       * 4621abc - sayma rtm: add clock mezzanine GPIO (#133) <hartytp>
   
   Full submodule status
   --
    5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
    a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
    5b02791580db9d1bae64b6524b7aca3540d89937 litedram (remotes/origin/HEAD)
    40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
    a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
    b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
    1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
    0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
    13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
    6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
    d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)

   

   mithro committed Oct 2, 2018
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2. Merge pull request #78 from mithro/litex-update …

   Updating submodules.

   

   mithro committed Oct 2, 2018
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