Also try to use return first on two first errors
as we do not know yet if we are being sourced or not.

 * edid-decode changed from 5eeb151 to 6def7bc
    * 6def7bc - edid-decode: make it easier to find the out-of-range monitor values <Hans Verkuil>

 * litedram changed from bc6a3f2 to 0572006
    * 0572006 - phy/kusddrphy: remove ResetSignal on ODELAYE3/ISERDESE3 that are dynamically adjusted, reduce sys latency <Florent Kermarrec>
    * 57ebcc5 - sdram_init/ddr4: enable dll <Florent Kermarrec>
    * 7a2ff33 - sdram_init/get_sdram_phy_py_header: generate mr1 value, fix init_sequence identation <Florent Kermarrec>
    * 33ff34b - core/refresher: use self.sync to fix build (verilog wire vs reg...) <Florent Kermarrec>
    * 8419f28 - core: split refresher, expose it and allow it to be reloaded externally. <Florent Kermarrec>
    * 8ec0bc6 - modules: improve the way we define DDR4 banks/groups <Florent Kermarrec>
    * 1618a76 - phy: add KUSDDRPHY to __init__.py <Florent Kermarrec>
    * d6350d9 - test/test_axi: reduce rand_level on writes <Florent Kermarrec>
    * 282b60e - frontend/axi: simplify LiteDRAMAXI2NativeW logic <Florent Kermarrec>
    * 6778c72 - test/test_axi: cleanup, all tests passings. <Florent Kermarrec>
    * ebb1d3c - frontend/axi/LiteDRAMAXI2NativeW: be sure that we already have the data before sending the command to the controller <Florent Kermarrec>
    * 0d5e554 - frontend/axi: expose aw_burst2beat/ar_burst2beat <Florent Kermarrec>
    * da65a80 - frontend/axi: expose w_buffer/r_buffer (can be useful for debug) <Florent Kermarrec>
    * 7f5d749 - test: add missing +x <Florent Kermarrec>
    * 7ef4869 - test/test_axi: also add randomness on rdata.valid and wdata.ready <Florent Kermarrec>
    * 3db68cd - test/test_axi/axi2native: add tests for each randomness parameters (ease finding regressions issues) <Florent Kermarrec>
    * 190b1bd - test/test_axi/axi2native: add finer control on randomness <Florent Kermarrec>
    * 4f137b9 - test/test_axi/axi2native: add random on len, just use writes as reads <Florent Kermarrec>
    * 2a799e4 - test/test_axi: set size on axi2native test <Florent Kermarrec>
    * e70d77e - phy/s7dddrphy: fix nphases = 2 (same code can be shared between nphases = 2 and nphases = 4) <Florent Kermarrec>
    * 170b3dc - frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI <Florent Kermarrec>
    * 9a25506 - frontend/wishbone: fix wishbone.err on LiteDRAMWishbone2AXI <Florent Kermarrec>

 * litepcie changed from dddd3b1 to b29c3a0
    * b29c3a0 - README: update PHY description <Florent Kermarrec>
    * 07501b8 - core: expose depacketizer/packetizer/controller (useful for debug) <Florent Kermarrec>
    * bfd2813 - frontend/dma: remove 64KB DMA buffer size limitation by increasing length to 24 bits. <Florent Kermarrec>

 * litex changed from v0.1-620-gab799f7b to v0.1-664-g0ade06c0
    *   0ade06c0 - Merge pull request #138 from mithro/mainram-hack <Tim Ansell>
    |\
    | * 22d454ef - Hack to fix #136. <Tim 'mithro' Ansell>
    |/
    *   fa6fef1e - Merge pull request #135 from mithro/icestorm-ice40up5k <Tim Ansell>
    |\
    | * 9481781d - Add uwg30 package and up3k part. <Tim 'mithro' Ansell>
    * | e9f10492 - soc/cores/cpu/vexriscv: add add_debug method for debug variants <Florent Kermarrec>
    * | 35155e51 - soc/cores/cpu/vexriscv: add support for the new variants. <Florent Kermarrec>
    * | 2ace45e6 - soc/cores/cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 6d6c2b4c - soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) <Florent Kermarrec>
    * | 584fd51c - build/sim/verilator: add support for plaform.sources, some cleanup <Florent Kermarrec>
    * | c9915f89 - build/microsemi/libero_soc: fix typos <Florent Kermarrec>
    * | 99578bc6 - gen/sim/core: add args support on Display <Florent Kermarrec>
    * | fa260f5b - gen/fhdl: add simulation Display, Finish support. <Florent Kermarrec>
    * | 92a6169d - build/sim: add coverage parameter to enable code coverage <Florent Kermarrec>
    * | 0c687bc2 - soc/interconnect/stream: add support for buffered async fifo <Florent Kermarrec>
    * | bf3b4eec - gen: integrate migen changes <Florent Kermarrec>
    |/
    * 96527b5a - soc/interconnect/stream/gearbox: remove bit reversing by changing words order <Florent Kermarrec>
    *   1c8c2426 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   cc4ba656 - Merge pull request #130 from jfng/master <enjoy-digital>
    | |\
    | | * 71398e01 - litex_sim: add --trace argument <Jean-François Nguyen>
    * | | 8887fc24 - build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build). <Florent Kermarrec>
    |/ /
    * | ec46beeb - targets/ulx3s, versa_ecp5: use ECP5PLL <Florent Kermarrec>
    * | 18048eb4 - cores/clock: test and fix ECP5PLL, phase still not implemented. <Florent Kermarrec>
    * | 20dd95c5 - boards/platforms/ulx3s: add gpios 0-3 <Florent Kermarrec>
    |/
    * 909cff19 - bios/sdram: flush l2 cache only when present <Florent Kermarrec>
    * 2ad83778 - bios: allow testing main_ram at init when using an external controller <Florent Kermarrec>
    * cdfe0454 - build/microsemi/libero_soc: small cleanup <Florent Kermarrec>
    *   4592e323 - Merge pull request #128 from mithro/small-fix <enjoy-digital>
    |\
    | * 4f565c51 - stream.Endpoint: Pass extra arguments to superclass. <Tim 'mithro' Ansell>
    | * 3b9e4c4d - wishbone.SRAM: Support non-32bit wishbone widths. <Tim 'mithro' Ansell>
    * 515c0621 - cores/clock: add ECP5PLL <Florent Kermarrec>
    * 7623b5dd - soc/interconnect/stream/gearbox: inverse bit order <Florent Kermarrec>
    * d32e3930 - soc/cores/spi_flash: add missing endianness parameter <Florent Kermarrec>
    * c954943e - platforms/avalanche: add IOStandard on ddram pins <Florent Kermarrec>
    * 09a1cda9 - build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification <Florent Kermarrec>
    * a98e1ad6 - build/microsemi/libero_soc: add additional_timing_constraints <Florent Kermarrec>
    * b1668823 - build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper <Florent Kermarrec>
    * 9df75d7d - platforms/avalanche: add package/speed to platform.device <Florent Kermarrec>
    * 953b1f70 - build/microsemi/libero_soc: remove previous impl directory if exists <Florent Kermarrec>
    * 18d513a1 - build/microsemi/libero_soc: give better names to pdc files: io/fp <Florent Kermarrec>
    * 4f092dbe - build/microsemi/libero_soc: add additional_constraints <Florent Kermarrec>
    * 206c9a46 - platforms/avalanche: fix ddram dq7 <Florent Kermarrec>
    * f0034077 - build/microsemi/libero_soc: add {} around port name. <Florent Kermarrec>
    * beeca856 - utils/litex_read_verilog: fix generated indent on instance <Florent Kermarrec>
    * 1fe7d09f - soc/integration/soc_core: add csr_map_update function <Florent Kermarrec>

 * migen changed from 0.6.dev-211-g022721a to 0.6.dev-228-g37db6bb
    * 37db6bb - Add uwg30 package and up3k part. <Tim 'mithro' Ansell>
    * abc2802 - fhdl/tracer: support Python 3.7 (#167) <Pierre-Olivier Vauboin>
    * e6ff283 - examples/sim: add display example <Florent Kermarrec>
    * 6742210 - sim/core: add Display support <Florent Kermarrec>
    * f46f014 - fhdl: add simulation Display, Finish support. <Florent Kermarrec>
    * 3d8a580 - build/lattice/icestorm: allow passing options to synth_ice40. <whitequark>
    * be608f9 - Revert "lattice/common: no need to differentiate nbits==1 and nbits > 1" <whitequark>
    * ac0dd18 - fhdl: give names to storage locations in MemoryToArray. <whitequark>
    * 01d9055 - fhdl: fix mismatch between _can_lower() and _lower_specials_step(). <whitequark>
    * f5005b5 - fhdl: append lowered specials to the original fragment. <whitequark>
    * 29b4e65 - genlib/resetsync: add __all__. <whitequark>
    * f0cd29f - genlib/fifo: add __all__. <whitequark>
    * c05fc0c - build/lattice/icestorm: add fine grained clock constraint support. <whitequark>
    * 0c57a44 - build/lattice/icestorm: simplify. <whitequark>
    * 4eca436 - fhdl/specials: allow passing name hint to TSTriple. <whitequark>
    * b5d723b - build/lattice/trellis: update for newer ecppack. <whitequark>
    * 3fc11b5 - build/lattice/icestorm: update package list for iCE40-HX8K. <Adam Greig>

Full submodule status
--
 6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (heads/master)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
 057200665f48fac184c46bbe6a82110f34ee01e4 litedram (heads/master)
 52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (heads/master)
 b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (heads/master)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
 0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (heads/master)
 0ade06c0f0b3ba747ceee5e35ea0abc7bc20df77 litex (v0.1-664-g0ade06c0)
 37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a migen (0.6.dev-228-g37db6bb)

Updating submodules.

Fixes in enter-env.sh script.

docs: Fix missing s