whitequark · Nov 20, 2018 · Nov 20, 2018 · Nov 20, 2018
Showing with 12 additions and 7 deletions.

+1 −0 .gitignore

+8 −5 software/glasgow/access/simulation/multiplexer.py

+1 −1 software/glasgow/applet/jtag/pinout.py

+2 −1 software/glasgow/applet/spi/flash_avr.py
diff --git a/.gitignore b/.gitignore
@@ -1,5 +1,6 @@
 __pycache__/
 *.egg-info/
+*.eggs/
 build/
 *.pyc
 *.v

diff --git a/software/glasgow/access/simulation/multiplexer.py b/software/glasgow/access/simulation/multiplexer.py
@@ -2,6 +2,7 @@
 from migen.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFOBuffered
 
 from .. import AccessMultiplexer, AccessMultiplexerInterface
+from ...gateware.fx2 import _FIFOWithFlush
 
 
 class SimulationMultiplexer(AccessMultiplexer):
@@ -29,16 +30,16 @@ def get_pin_name(self, pin):
     def build_pin_tristate(self, pin, oe, o, i):
         pass
 
-    def _make_fifo(self, arbiter_side, logic_side, cd_logic, depth):
+    def _make_fifo(self, arbiter_side, logic_side, cd_logic, depth, wrapper=lambda x: x):
         if cd_logic is None:
-            fifo = SyncFIFOBuffered(8, depth)
+            fifo = wrapper(SyncFIFOBuffered(8, depth))
         else:
             assert isinstance(cd_logic, ClockDomain)
 
-            fifo = ClockDomainsRenamer({
+            fifo = wrapper(ClockDomainsRenamer({
                 arbiter_side: "sys",
                 logic_side:   "logic",
-            })(AsyncFIFO(8, depth))
+            })(AsyncFIFO(8, depth)))
 
             fifo.clock_domains.cd_logic = ClockDomain()
             self.comb += fifo.cd_logic.clk.eq(cd_logic.clk)
@@ -51,7 +52,9 @@ def get_in_fifo(self, depth=512, auto_flush=False, clock_domain=None):
         assert self.in_fifo is None
 
         self.submodules.in_fifo = self._make_fifo(
-            arbiter_side="read", logic_side="write", cd_logic=clock_domain, depth=depth)
+            arbiter_side="read", logic_side="write", cd_logic=clock_domain, depth=depth,
+            wrapper=lambda x: _FIFOWithFlush(x, async=clock_domain is not None,
+                                             auto_flush=auto_flush))
         return self.in_fifo
 
     def get_out_fifo(self, depth=512, clock_domain=None):

diff --git a/software/glasgow/applet/jtag/pinout.py b/software/glasgow/applet/jtag/pinout.py
@@ -292,4 +292,4 @@ async def interact(self, device, args, iface):
 class JTAGPinoutAppletTestCase(GlasgowAppletTestCase, applet=JTAGPinoutApplet):
     @synthesis_test
     def test_build(self):
-        self.assertBuilds()
+        self.assertBuilds(args=["--pins-jtag", "0:3"])
diff --git a/software/glasgow/applet/spi/flash_avr.py b/software/glasgow/applet/spi/flash_avr.py
@@ -1,4 +1,5 @@
 import time
+import math
 import struct
 import logging
 import asyncio
@@ -269,7 +270,7 @@ def build(self, target, args):
             pads=iface.get_pads(args, pins=self.__pins),
             out_fifo=iface.get_out_fifo(),
             in_fifo=iface.get_in_fifo(),
-            bit_rate=args.bit_rate * 1000,
+            period_cyc=math.ceil(target.sys_clk_freq / (args.bit_rate * 1000)),
             sck_idle=0,
             sck_edge="rising",
             ss_active=0,