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base repository: whitequark/glasgow
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head repository: whitequark/glasgow
compare: 8f88f5ba97a0
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  • 1 commit
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  • 1 contributor

Commits on Dec 4, 2018

  1. gateware.boneless: ensure sensible names in Verilog output (-2 LUT). 

    Not sure where the LUTs have gone, but I'll take it.
    @whitequark
    whitequark committed Dec 4, 2018
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