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base repository: whitequark/glasgow
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head repository: whitequark/glasgow
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compare: c7aee002439d
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 3, 2018

  1. gateware.boneless: implement LDI and STI.

    @whitequark
    whitequark committed Dec 3, 2018
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    954b237 View commit details

  2. gateware.boneless: implement JAL and JR.

    @whitequark
    whitequark committed Dec 3, 2018
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    c7aee00 View commit details
Showing with 72 additions and 22 deletions.
  1. +2 −2 software/glasgow/arch/boneless/__init__.py
  2. +70 −20 software/glasgow/gateware/boneless.py
4 changes: 2 additions & 2 deletions software/glasgow/arch/boneless/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -111,10 +111,10 @@
# - code=000 MOVL
# - code=001 MOVH
# - code=010 MOVA
# - code=011 JAL
# - code=011 ADDI/SUBI
# - code=100 LDI
# - code=101 STI
# - code=110 ADDI/SUBI
# - code=110 JAL
# - code=111 JR
# * class=C
# - code=000
90 changes: 70 additions & 20 deletions software/glasgow/gateware/boneless.py
View file
Original file line number Diff line number Diff line change
@@ -123,18 +123,18 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
If(i_clsA,
mem_port.adr.eq(Cat(i_regX, r_win)),
mem_port.re.eq(1),
NextState("A-LOAD")
NextState("A-READ")
).Elif(i_clsS,
mem_port.adr.eq(Cat(i_regY, r_win)),
mem_port.re.eq(1),
NextState("S-LOAD")
NextState("S-READ")
).Elif(i_clsM,
mem_port.adr.eq(Cat(i_regY, r_win)),
mem_port.re.eq(1),
If(i_store,
NextState("M-LOAD")
If(~i_store,
NextState("M/I-LOAD-1")
).Else(
NextState("M-READ")
NextState("M/I-STORE-1")
)
).Elif(i_clsI,
mem_port.adr.eq(Cat(i_regZ, r_win)),
@@ -144,10 +144,10 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
OPCODE_MOVH: NextState("I-EXECUTE-MOVx/ADDI"),
OPCODE_MOVA: NextState("I-EXECUTE-MOVx/ADDI"),
OPCODE_ADDI: NextState("I-EXECUTE-MOVx/ADDI"),
# OPCODE_LDI: NextState(),
# OPCODE_STI: NextState(),
# OPCODE_JAL: NextState(),
# OPCODE_JR: NextState(),
OPCODE_LDI: NextState("M/I-LOAD-1"),
OPCODE_STI: NextState("M/I-STORE-1"),
OPCODE_JAL: NextState("I-EXECUTE-Jx"),
OPCODE_JR: NextState("I-EXECUTE-Jx"),
})
).Elif(i_clsC,
If(s_cond == i_flag,
@@ -159,7 +159,7 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
)
)
)
self.fsm.act("A-LOAD",
self.fsm.act("A-READ",
mem_port.adr.eq(Cat(i_regY, r_win)),
mem_port.re.eq(1),
NextValue(r_opA, mem_port.dat_r),
@@ -185,7 +185,7 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
c_flags.eq(1),
NextState("FETCH")
)
self.fsm.act("S-LOAD",
self.fsm.act("S-READ",
NextValue(r_opS, mem_port.dat_r),
NextValue(r_shift, i_shift),
NextState("S-EXECUTE")
@@ -211,27 +211,35 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
NextState("FETCH")
)
)
self.fsm.act("M-READ",
s_addr.eq(AddSignedImm(mem_port.dat_r, i_imm5)),
self.fsm.act("M/I-LOAD-1",
If(i_clsI,
s_addr.eq(AddSignedImm(r_pc, i_imm8))
).Else(
s_addr.eq(AddSignedImm(mem_port.dat_r, i_imm5))
),
mem_port.adr.eq(s_addr),
mem_port.re.eq(~i_ext),
ext_port.adr.eq(s_addr),
ext_port.re.eq(i_ext),
NextState("M-STORE")
NextState("M/I-LOAD-2")
)
self.fsm.act("M-STORE",
self.fsm.act("M/I-LOAD-2",
mem_port.adr.eq(Cat(i_regZ, r_win)),
mem_port.dat_w.eq(Mux(i_ext, ext_port.dat_r, mem_port.dat_r)),
mem_port.we.eq(1),
NextState("FETCH")
)
self.fsm.act("M-LOAD",
NextValue(r_addr, AddSignedImm(mem_port.dat_r, i_imm5)),
self.fsm.act("M/I-STORE-1",
If(i_clsI,
NextValue(r_addr, AddSignedImm(r_pc, i_imm8))
).Else(
NextValue(r_addr, AddSignedImm(mem_port.dat_r, i_imm5))
),
mem_port.adr.eq(Cat(i_regZ, r_win)),
mem_port.re.eq(1),
NextState("M-WRITE")
NextState("M/I-STORE-2")
)
self.fsm.act("M-WRITE",
self.fsm.act("M/I-STORE-2",
mem_port.adr.eq(r_addr),
mem_port.dat_w.eq(mem_port.dat_r),
mem_port.we.eq(~i_ext),
@@ -242,7 +250,7 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
)
self.fsm.act("I-EXECUTE-MOVx/ADDI",
mem_port.adr.eq(Cat(i_regZ, r_win)),
Case(Cat(i_code2, C(0, 1), C(OPCLASS_I, 2)), {
Case(Cat(i_code2, C(0b0, 1), C(OPCLASS_I, 2)), {
OPCODE_MOVL: mem_port.dat_w.eq(Cat(i_imm8, C(0, 8))),
OPCODE_MOVH: mem_port.dat_w.eq(Cat(C(0, 8), i_imm8)),
OPCODE_MOVA: mem_port.dat_w.eq(AddSignedImm(r_pc, i_imm8)),
@@ -251,6 +259,15 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
mem_port.we.eq(1),
NextState("FETCH")
)
self.fsm.act("I-EXECUTE-Jx",
mem_port.adr.eq(Cat(i_regZ, r_win)),
mem_port.dat_w.eq(r_pc),
Case(Cat(i_code1, C(0b11, 2), C(OPCLASS_I, 2)), {
OPCODE_JAL: [NextValue(r_pc, AddSignedImm(r_pc, i_imm11)), mem_port.we.eq(1)],
OPCODE_JR: [NextValue(r_pc, AddSignedImm(mem_port.dat_r, i_imm11))]
}),
NextState("FETCH")
)
self.fsm.act("HALT",
NextState("HALT")
)
@@ -487,3 +504,36 @@ def test_MOVI(self, tb):
yield from self.assertMemory(tb, 0, 0x0012)
yield from self.assertMemory(tb, 1, 0x1234)
yield from self.assertMemory(tb, 2, 0x89ab)

@simulation_test(regs=[0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x1234, 0x0000],
code=[LDI (R0, -3)])
def test_LDI(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x1234)

@simulation_test(regs=[0x1234, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000],
code=[STI (R0, -3)])
def test_STI(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 6, 0x1234)

@simulation_test(code=[JAL (R0, 1),
MOVL(R1, 1),
MOVL(R2, 1)])
def test_JAL(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x0009)
yield from self.assertMemory(tb, 1, 0x0000)
yield from self.assertMemory(tb, 2, 0x0001)

@simulation_test(regs=[0x0004],
code=[JR (R0, 6),
MOVL(R1, 1),
MOVL(R2, 1)])
def test_JR(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x0004)
yield from self.assertMemory(tb, 1, 0x0000)
yield from self.assertMemory(tb, 2, 0x0001)