gateware.boneless: use non-transparent read port (-47 LUT, -17 DFF).

Before: Number of wires: 462 Number of wire bits: 899 Number of public wires: 44 Number of public wire bits: 386 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 717 SB_CARRY 93 SB_DFF 1 SB_DFFE 1 SB_DFFESR 80 SB_DFFSR 36 SB_LUT4 505 SB_RAM40_4K 1 After: Number of wires: 416 Number of wire bits: 868 Number of public wires: 45 Number of public wire bits: 402 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 670 SB_CARRY 93 SB_DFF 1 SB_DFFE 1 SB_DFFESR 80 SB_DFFSR 19 SB_LUT4 475 SB_RAM40_4K 1
whitequark · Dec 4, 2018 · cb4b55b · cb4b55b
1 parent b8c4939
commit cb4b55b
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/software/glasgow/gateware/boneless.py b/software/glasgow/gateware/boneless.py
@@ -285,8 +285,8 @@ def do_finalize(self):
         self.mem = Memory(width=16, depth=len(self.mem_init), init=self.mem_init)
         self.specials += self.mem
 
-        mem_rdport = self.mem.get_port(has_re=True)
-        mem_wrport = self.mem.get_port(has_re=True, write_capable=True)
+        mem_rdport = self.mem.get_port(has_re=True, mode=READ_FIRST)
+        mem_wrport = self.mem.get_port(write_capable=True)
         self.specials += [mem_rdport, mem_wrport]
 
         if self.ext_init:
@@ -699,8 +699,8 @@ def __init__(self, has_pins=False):
             ]
 
         self.specials.mem = Memory(width=16, depth=256)
-        self.specials.mem_rdport = self.mem.get_port(has_re=True)
-        self.specials.mem_wrport = self.mem.get_port(has_re=True, write_capable=True)
+        self.specials.mem_rdport = self.mem.get_port(has_re=True, mode=READ_FIRST)
+        self.specials.mem_wrport = self.mem.get_port(write_capable=True)
         self.submodules.dut = BonelessCore(reset_addr=8,
             mem_rdport=self.mem_rdport,
             mem_wrport=self.mem_wrport,