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base repository: whitequark/glasgow
base: f4836da0723e
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head repository: whitequark/glasgow
compare: cb4b55b9d623
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 4, 2018

  1. gateware.boneless: use split memory ports, if any (-20 LUT). 

    Before:
   Number of wires:                475
   Number of wire bits:            919
   Number of public wires:          44
   Number of public wire bits:     386
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                737
     SB_CARRY                       93
     SB_DFF                          9
     SB_DFFE                         1
     SB_DFFESR                      80
     SB_DFFSR                       36
     SB_LUT4                       517
     SB_RAM40_4K                     1

After:
   Number of wires:                462
   Number of wire bits:            899
   Number of public wires:          44
   Number of public wire bits:     386
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                717
     SB_CARRY                       93
     SB_DFF                          1
     SB_DFFE                         1
     SB_DFFESR                      80
     SB_DFFSR                       36
     SB_LUT4                       505
     SB_RAM40_4K                     1
    @whitequark
    whitequark committed Dec 4, 2018
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    b8c4939 View commit details
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  2. gateware.boneless: use non-transparent read port (-47 LUT, -17 DFF). 

    Before:
   Number of wires:                462
   Number of wire bits:            899
   Number of public wires:          44
   Number of public wire bits:     386
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                717
     SB_CARRY                       93
     SB_DFF                          1
     SB_DFFE                         1
     SB_DFFESR                      80
     SB_DFFSR                       36
     SB_LUT4                       505
     SB_RAM40_4K                     1

After:
   Number of wires:                416
   Number of wire bits:            868
   Number of public wires:          45
   Number of public wire bits:     402
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                670
     SB_CARRY                       93
     SB_DFF                          1
     SB_DFFE                         1
     SB_DFFESR                      80
     SB_DFFSR                       19
     SB_LUT4                       475
     SB_RAM40_4K                     1
    @whitequark
    whitequark committed Dec 4, 2018
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    cb4b55b View commit details
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