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base repository: m-labs/nmigen
base: 27d3dfc45374
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head repository: m-labs/nmigen
compare: 5b8708017e52
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 13, 2018

  1. back.verilog: detect undriven public wires using Yosys. 

    This should never happen, and is certainly a logic bug in nMigen.
    whitequark committed Dec 13, 2018
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    4e32f6b View commit details
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  2. fhdl.ast: fix Switch._?hs_signals() for switch without statements.

    whitequark committed Dec 13, 2018
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