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base repository: timvideos/HDMI2USB-litex-firmware
base: 57fb821eba48
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head repository: timvideos/HDMI2USB-litex-firmware
compare: a33050bfddce
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  • 14 commits
  • 14 files changed
  • 2 contributors

Commits on Oct 28, 2018

  1. Updating submodules. 

     * litedram changed from 5b02791 to f36bcff
    * f36bcff - phy/gensdrphy: cleanup/simplify pass <Florent Kermarrec>
    * da06715 - core/bankmachine: typo <Florent Kermarrec>
    * ab0d519 - core: change cba_shift parameter to more explicit address_mapping parameter <Florent Kermarrec>
    * 230ea24 - core: simplify/cleanup pass <Florent Kermarrec>
    * 94b844d - core/frontend: move crossbar to core <Florent Kermarrec>
    * 8d24163 - phy/s7ddrphy: use our own bitslip module in fabric <Florent Kermarrec>
    * 20d7675 - phy/s7ddrphy: add additional_read_latency parameter <Florent Kermarrec>
    * f11506a - examples/litedram_gen: cleanup pins definition <Florent Kermarrec>
    * 75b314c - modules: update K4B2G1646F and use timings from datasheet <Florent Kermarrec>
    * b71ed35 - core/bankmachine: manage tRC <Florent Kermarrec>
    * 0abb3e4 - modules: use tRAS and tRP to compute tRC (tRC = tRAS + tRP) <Florent Kermarrec>
    * 9a950f0 - ecc: update core/test <Florent Kermarrec>
    * 8a0d0f0 - phy/s7ddrphy: remove hacky bl8 variant (see #60) <Florent Kermarrec>
    * 5fe4868 - modules: add trrd to all ddr3 modules <Florent Kermarrec>
    *   dbfa929 - Merge pull request #59 from enjoy-digital/tRRD_Fix <enjoy-digital>
    |\
    | * 5315d27 - tRRD incorrectly specified <john@csquare.ca>
    |/
    * 167c0c9 - remove partial reordering code in master, keep things in bank_reordering branch. <Florent Kermarrec>
    * 828129e - core/bank_machine: simplify trascon <Florent Kermarrec>
    * 4fa64c8 - core/bankmachine: remove trccon (activate_allowed not used) <Florent Kermarrec>
    * feac98f - core/bankmachine: use tXXDController everywhere (better timings) <John Sully>
    * bce411e - common: move tXXDController to common <John Sully>
    * fef4701 - core/multiplexer: select all ranks on refresh <Florent Kermarrec>
    * 3481d45 - core/multiplexer: fix rank_decoder width <Florent Kermarrec>
    * 3b5a1ff - modules: add K4B1G0446F <Florent Kermarrec>
    * 48c17ce - modules: fix tWTR regression on MT46H32M32 <Florent Kermarrec>
    * ad0a1d4 - modules: improve timings definition (keep retro-compatibility with previous definitions) <Florent Kermarrec>

 * litepcie changed from a09d225 to a8b8048
    * a8b8048 - core/tlp/reordering: increase buffering <Florent Kermarrec>
    * 9578a3c - LICENSE: typo <Florent Kermarrec>
    * b37065c - Merge pull request #13 from enjoy-digital/reordering <enjoy-digital>
    * 62d6217 - core/tlp/reordering: use buffered=True <Florent Kermarrec>
    * 35a4aa8 - core/tlp/reordering: use buffered data fifo to ease timings <Florent Kermarrec>
    * 288c5f9 - core/tlp/reordering: refactor/simplify <Florent Kermarrec>
    * 1f39ee2 - core/tlp/controller: use log2_int everywhere <Florent Kermarrec>

 * litex changed from 6e327cda to 3e189379
    * 3e189379 - boards/targets: add versa ecp55g prjtrellis target (experimental) <Florent Kermarrec>
    * a69197d2 - build/lattice: add initial prjtrellis support <Florent Kermarrec>
    * 397e3c76 - build/lattice/diamond: use bash on linux <Florent Kermarrec>
    * d029cd24 - build/lattice: improve special_overrides names (vendor_family) <Florent Kermarrec>
    *   60665358 - Merge pull request #114 from mithro/xilinx+yosys <enjoy-digital>
    |\
    | *   b200ce99 - Merge branch 'master' into xilinx+yosys <enjoy-digital>
    | |\
    | |/
    |/|
    * |   8c0982a1 - Merge pull request #118 from mithro/uart-sync <enjoy-digital>
    |\ \
    | * | ba0dd572 - uart: Enable buffering the FIFO. <Tim 'mithro' Ansell>
    |/ /
    * | f9167053 - README: improve instructions for litex_sim <Florent Kermarrec>
    * | e3935b48 - build/sim/verilator: don't use THEADS parameters when threads=1 <Florent Kermarrec>
    * | a44181e7 - soc_sdram: update litedram <Florent Kermarrec>
    * | ab6a530a - bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode <Florent Kermarrec>
    * | b8be9545 - build/xilinx/vivado: enable xpm libraries <Florent Kermarrec>
    * | ab8cf3e3 - soc/cores/clock: add margin parameter to create_clkout (default = 1%) <Florent Kermarrec>
    * | 915c2f41 - bios/sdram: improve write/read leveling <Florent Kermarrec>
    * | deffa603 - platforms/kc705: add ddram_dual_rank <Florent Kermarrec>
    * | 10624c26 - bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) <Florent Kermarrec>
    * |   9f083e9b - Merge pull request #116 from stffrdhrn/sim-uart <enjoy-digital>
    |\ \
    | * | 8877dba7 - sim: serial: Send '\r\n' instead of just '\n' <Stafford Horne>
    |  /
    * | d1879215 - cpu_interface: fix select_triple when only one specified <Florent Kermarrec>
    * | 3b27d2ae - soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains <Florent Kermarrec>
    * | 168b07b9 - soc_core: add csr range check <Florent Kermarrec>
    * |   6febb682 - Merge pull request #112 from cr1901/8k-b-evn <enjoy-digital>
    |\ \
    | * | 9a44f08a - build/platforms: Add ice40_hx8k_b_evn from Migen. <William D. Jones>
    |  /
    * |   9cf4ffb3 - Merge pull request #113 from stffrdhrn/litex-trivial <enjoy-digital>
    |\ \
    | * | ff6de429 - Fix help for or1k builds <Stafford Horne>
    | * | dafdb8df - Fix compiler warnings from GCC 8.1 <Stafford Horne>
    |/ /
    * | 2be52054 - build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) <Florent Kermarrec>
    | * ace97624 - build.xilinx: Convert attributes to something Yosys understands. <Tim 'mithro' Ansell>
    | * 78414c05 - xilinx/viviado: Allow yosys for synthesis. <Tim 'mithro' Ansell>
    | * d13ac3b3 - cpu/mor1kx: Adding verilog include directory. <Tim 'mithro' Ansell>
    | * dc7cd757 - build.xilinx: Run `phys_opt_design` and generate timing report. <Tim 'mithro' Ansell>
    |/
    * 948527b0 - cores/cpu: revert vexriscv (it seems there is a regression in last version) <Florent Kermarrec>
    * 15bca453 - targets/sim: fix integrated_main_ram_size when with_sdram <Florent Kermarrec>

 * migen changed from 0.6.dev-173-gd3b875b to 0.6.dev-179-g657c0c7
    * 657c0c7 - class TSTriple: width is the width of the base signal <Staf Verhaegen>
    * 2d62c0c - platforms/ice40_up5k_b_evn: Add I/O connector and some default I/O (including spiflash). <William D. Jones>
    * ea6e483 - Fix issue where BusSynchronizer fails when iclock << oclock <bunnie>
    * 076ec0d - fhdl.visit: fix nondeterminism in visit_Case. <whitequark>
    * 1e114c7 - add a print to show user context when an exception is raised while evaluating a generator yield statement in simulation <N. Engelhardt>
    * ba63364 - platforms/ice40_hx8k_b_evn: Add pins for spiflash io. <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 f36bcff49fe96867503c219dd705ff8d7eb951cd litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a8b804809d84e2125eb603bf9feefc9cef31d22b litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 3e189379f9272ba184fcdcfe077eb139f1f0fc7f litex (heads/master)
 657c0c72e63597162837809dfe3635d69a98cfd9 migen (0.6.dev-179-g657c0c7)
    @cr1901
    cr1901 committed Oct 28, 2018
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Commits on Oct 29, 2018

  1. gateware/cas: Add RGB LED support (treat as user_leds).

    @cr1901
    cr1901 committed Oct 29, 2018
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  2. platforms/ice40_up5k_b_evn: Move default serial port mapping to free … 

    …pins (previous pins shared with switches).
    @cr1901
    cr1901 committed Oct 29, 2018
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  3. targets/ice40_up5k_b_evn: Enable CAS module. Closes #92.

    @cr1901
    cr1901 committed Oct 29, 2018
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  4. Add PMOD connections for USB UART, use as default serial port for now.

    @cr1901
    cr1901 committed Oct 29, 2018
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  5. Merge pull request #93 from cr1901/up5k-leds 

    Add RGB LED support to ICE40UP5K-B-EVN Target
    @mithro
    mithro committed Oct 29, 2018
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  6. Updating submodules. 

     * litex changed from v0.1-528-g3e189379 to v0.1-532-g98159209
    *   98159209 - Merge pull request #120 from mithro/master <Tim Ansell>
    |\
    | * 1cac079e - litex/build: Always run Vivado. <Tim 'mithro' Ansell>
    |/
    * 49dab3b4 - build/lattice/prjtrellis: simplify code, remove some workarounds <Florent Kermarrec>
    * a73d9d96 - build/xilinx/vivado: fix merge issue <Florent Kermarrec>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 f36bcff49fe96867503c219dd705ff8d7eb951cd litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a8b804809d84e2125eb603bf9feefc9cef31d22b litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 9815920946d348bb81fe013413c6f8b6cd472a93 litex (v0.1-532-g98159209)
 657c0c72e63597162837809dfe3635d69a98cfd9 migen (0.6.dev-179-g657c0c7)
    @mithro
    mithro committed Oct 29, 2018
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Commits on Oct 31, 2018

  1. platforms: Add icebreaker platform with base target. Micropython boots.

    @cr1901
    cr1901 committed Oct 31, 2018
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  2. Merge pull request #95 from cr1901/icebreaker 

    platforms: Add icebreaker platform with base target. Micropython boots.
    @mithro
    mithro committed Oct 31, 2018
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Commits on Nov 13, 2018

  1. tinyfpga_bx: Actually use pins documented. 

     * Remove duplicate entry in `targets/tinyfpga_bx.py`.
 * Add useful comments.
    @mithro
    mithro committed Nov 13, 2018
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  2. tinyfpga_bx: Adding better documentation.

    @mithro
    mithro committed Nov 13, 2018
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  3. Merge pull request #101 from mithro/master 

    tinyfpga_bx: Actually use pins documented.
    @mithro
    mithro committed Nov 13, 2018
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Commits on Nov 14, 2018

  1. Updating submodules. 

     * litedram changed from f36bcff to 30d9a3e
    * 30d9a3e - modules: add MT40A1G8 DDR4 <Florent Kermarrec>
    * 4459bd2 - frontend/axi: same condition to connect connect wdata.we and wdata <Florent Kermarrec>
    * d10e2e9 - core: make address_mapping a controller setting <Florent Kermarrec>
    * 7973b7d - frontend/axi: emits the write command only if we have the write data <Florent Kermarrec>
    * 6fa891d - frontend/axi: fix write response for bursts <Florent Kermarrec>
    * 93e8510 - test/test_axi: add bursts to axi2native <Florent Kermarrec>
    * e27fbc2 - test/test_axi: move definitions to top and make Access herit from Burst <Florent Kermarrec>
    * 4470f32 - test/test_axi: change order of the tests <Florent Kermarrec>
    * 070cc26 - test/test_axi: use separate generator for writes cmd/data <Florent Kermarrec>
    * 127e928 - frontend/wishbone: simplify LiteDRAMWishbone2Native code (resource usage almost the same) <Florent Kermarrec>
    * ca82ac1 - frontend/wishbone: add LiteDRAMWishbone2AXI <Florent Kermarrec>
    * 3586e15 - frontend/axi: improve len/size comment (-1), set default id_width to 1 <Florent Kermarrec>
    * 71be616 - frontend/axi: be sure wdata is available before sending the command to the controller <Florent Kermarrec>
    * 55b5f40 - modules: add AS4C256M16D3A <Florent Kermarrec>
    *   69ea866 - Merge pull request #62 from daveshah1/AS4C32M16 <enjoy-digital>
    |\
    | * 3a5d45b - modules: Add AS4C32M16 32Mx16 SDRAM <David Shah>
    * | b41fe61 - phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering <Florent Kermarrec>
    * | 2e19787 - phy/kusddrphy: add dfi mux on address/control signals <Florent Kermarrec>
    * | a8c3d39 - sdram_init: fix compilation <Florent Kermarrec>
    * | af34489 - common: add DDR4 burst_length <Florent Kermarrec>
    * | 2a9fb11 - phy/kusddrphy: more genericity, initial DDR4 support <Florent Kermarrec>
    * | ae5dc9f - sdram_init: add initial DDR4 initialization <Florent Kermarrec>
    * | 8181fea - modules: add EDY4016A DDR4 <Florent Kermarrec>
    * | 346e64c - frontend/ecc: fix typo <Florent Kermarrec>
    |/
    * 82c08c7 - phy/gensdrphy: use tristate input <Florent Kermarrec>
    * 9ce84d9 - modules: add MT48LC16M16 (ulx3s) <Florent Kermarrec>

 * liteeth changed from 40b99ec to 52c2301
    * 52c2301 - frontend/etherbone: reduce default buffer_depth to 4 <Florent Kermarrec>
    * 602ddec - common: use reverse_bytes from litex.gen <Florent Kermarrec>

 * litepcie changed from a8b8048 to 48f662e
    * 48f662e - phy/s7pciephy: force user to use register_pll1 if pll1 is needed <Florent Kermarrec>
    * 33f4601 - phy/s7pciephy: add register_pll1 method <Florent Kermarrec>
    * 80f28b1 - common: use reverse_bits/reverse_bytes from litex.gen <Florent Kermarrec>

 * litex changed from v0.1-532-g98159209 to v0.1-602-gbc173380
    *   bc173380 - Merge pull request #126 from mithro/toolchain-fix <Tim Ansell>
    |\
    | * b1425ba8 - lattice/icestorm: Add toolchain_path so it doesn't end up kwargs. <Tim 'mithro' Ansell>
    |/
    * af25bf2b - soc_core: check for cpu before checking interrupt <Florent Kermarrec>
    * b4bdf2a0 - cores/clock/S7: just reset the generated clock, not the PLL/MMCM <Florent Kermarrec>
    * 86fd945b - bios/main: fix typo on mor1kx <Florent Kermarrec>
    * af950285 - cpu/mor1kx: use clang only for linux variant <Florent Kermarrec>
    * 04523bc2 - xilinx/vivado: fix migen merge <Florent Kermarrec>
    * f3343c46 - platforms: remove versaecp55g_sdram <Florent Kermarrec>
    * 58414b18 - build/xilinx/vivado: merge migen change <Florent Kermarrec>
    * a7f17f99 - build: use default toolchain_path on all backend when passed value is None <Florent Kermarrec>
    * eed1d5cb - generic_platform: use set for sources <Florent Kermarrec>
    * 665fff83 - build: merge more migen changes <Florent Kermarrec>
    * 70f48775 - platforms/versa_ecp5: import migen changes <Florent Kermarrec>
    * 4ff241b9 - targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis <Florent Kermarrec>
    * cb86728a - build/lattice: import changes from migen <Florent Kermarrec>
    * 8574c62f - targets/versa_ecp5: increase sys_clk_freq to 50MHz <Florent Kermarrec>
    * a752dafb - targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll <Florent Kermarrec>
    * 87c7d23d - targets/ulx3s: for now revert to 25MHz clock/no pll <Florent Kermarrec>
    * d1baae36 - platforms/versa_ecp5: add ecp5 soc hat ios <Florent Kermarrec>
    *   b3bf1c95 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   1be6762d - Merge pull request #125 from daveshah1/trellis_sdram <enjoy-digital>
    | |\
    | | * f08f80be - working on Versa-5G dram <David Shah>
    | | * d78d5d3e - Debugging ULX3S SDRAM <David Shah>
    * | | 425ad755 - plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5 <Florent Kermarrec>
    |/ /
    * | c57aa545 - targets/ulx3s: get memtest working by disabling sdram refresh <Florent Kermarrec>
    * | 9a644717 - soc/integration/soc_sdram: allow using axi interface with litedram <Florent Kermarrec>
    * | 416bdb64 - boards/platforms: add avalanche polarfire board ios definition <Florent Kermarrec>
    * | fc0d5c39 - bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients <Florent Kermarrec>
    * | 09f962fd - target/kcu105: add reset button <Florent Kermarrec>
    * | 169f8d8c - boards/platforms/kcu105: fix sdram/dq pin swap <Florent Kermarrec>
    * | 2624ba48 - bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 <Florent Kermarrec>
    * | 6be74aa1 - boards/targets: add kcu105 <Florent Kermarrec>
    * |   93c62325 - Merge pull request #122 from daveshah1/trellis_ulx3s <enjoy-digital>
    |\ \
    | |/
    | * 0729b3a0 - ulx3s: Connect SDRAM clock <David Shah>
    | * 84044349 - Fix Trellis build; ULX3S demo boots to BIOS <David Shah>
    | * 0c1d8d59 - trellis: Switch to using LPF for constraints <David Shah>
    * |   00ef8240 - Merge pull request #124 from jfng/master <enjoy-digital>
    |\ \
    | * | dcbe759b - build/sim/verilator: don't use --threads when $(THREADS) is unset <Jean-François Nguyen>
    |/ /
    * | 6f38213a - boards/platforms/kc705: add user_sma_mgt_refclk <Florent Kermarrec>
    * |   4cdd6799 - Merge pull request #123 from cr1901/prv32-min <enjoy-digital>
    |\ \
    | * | e56f7182 - libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). <William D. Jones>
    | * | f32121e0 - cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. <William D. Jones>
    | * | 77389d27 - libbase/crt0-picorv32: Ensure BSS is cleared on boot. <William D. Jones>
    | * | f69bd877 - cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). <William D. Jones>
    | * | d05fe673 - cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. <William D. Jones>
    * | | f7969b66 - cores/clock: add with_reset parameter (default to True) <Florent Kermarrec>
    | |/
    |/|
    * | 445c4940 - boards/platforms/kcu105: add sfp_tx/rx definition <Florent Kermarrec>
    |/
    * e9d4c882 - build/lattice/prjtrellis: fix default toolchain_path <Florent Kermarrec>
    * 468780c0 - soc/cores/spi_flash: add endianness parameter <Florent Kermarrec>
    * 6f3131e2 - soc/interconnect/stream_packet: use reverse_bytes from litex.gen <Florent Kermarrec>
    * b7968538 - gen: add common with reverse_bits/reverse_bytes functions <Florent Kermarrec>
    * 71fc34d7 - boards/targets/ulx3s: reduce l2_size <Florent Kermarrec>
    * 75d073f3 - build/lattice/prjtrellis: fix typo <Florent Kermarrec>
    * 6048a529 - build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts. <Florent Kermarrec>
    * 2243f628 - build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl <Florent Kermarrec>
    *   3a8bb94a - Merge pull request #121 from cr1901/patch-3 <Tim Ansell>
    |\
    | * f3111e11 - Update vivado.py <William D. Jones>
    |/
    * 98fa8996 - boards/targets: add ulx3s <Florent Kermarrec>
    * 7d779473 - boards/platforms: add ulx3s <Florent Kermarrec>
    * d9dcad33 - build/lattice/prjtrellis: add inout support <Florent Kermarrec>
    * 091ad799 - build/lattice/common: add tristate support <Florent Kermarrec>
    * 23acefb1 - boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed <Florent Kermarrec>
    * 1097f822 - build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis" <Florent Kermarrec>
    * 52917a71 - boards/targets/simple: add gateware-toolchain parameter <Florent Kermarrec>
    * d84083f6 - boards/platforms/versaecp55g: use ftdi serial pins <Florent Kermarrec>
    * c05b9ef2 - build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support <Florent Kermarrec>
    * a8f819fe - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 4eb314a2 - boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :) <Florent Kermarrec>
    * 27ec2a59 - build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO <Florent Kermarrec>
    * c506c975 - gen/fhdl/verilog: set direction to io signals <Florent Kermarrec>

 * migen changed from 0.6.dev-179-g657c0c7 to 0.6.dev-209-gc285c12
    * c285c12 - genlib/fsm: allow subclassing FSM and overriding control functionality. <whitequark>
    * dd78f38 - sim/core: fix typo breaking `yield x.part(...).eq(...)`. <whitequark>
    * f8bea17 - test/test_fsm: fix typo. <whitequark>
    * 319d3cd - build: use default toolchain_path on all backends when toolchain_path passed value is None <Florent Kermarrec>
    * e7c9ab0 - xilinx/vivado: fix missing **kwargs <Florent Kermarrec>
    * 8789575 - xilinx/vivado: fix edifs/ips import <Florent Kermarrec>
    * 5851076 - build: make sure build_name/kwargs are passed to platform.get_verilog on all backends <Florent Kermarrec>
    * ec40e98 - xilinx/vivado: enable xpm libraries <Florent Kermarrec>
    * 21bb0f7 - xilinx/vivado: add support for importing edifs for ips <Florent Kermarrec>
    * 263e729 - xilinx/programmer: add device parameter <Florent Kermarrec>
    * f71b4a8 - xilinx/ise: set build_name as top name <Florent Kermarrec>
    * 2dc085d - lattice/common: no need to differentiate nbits==1 and nbits > 1 <Florent Kermarrec>
    * 48023fa - lattice: fix Misc constraints <Florent Kermarrec>
    * 1fdf5db - lattice/diamond: use build_name as top name <Florent Kermarrec>
    * 28a5f32 - genlib/fsm: add basic FSM tests. <whitequark>
    * 9cd4e2c - remove asic_syntax and other cleanups <Sebastien Bourdeauducq>
    * cf4c3ef - build/lattice/diamond: translate `keep` and `no_retiming` attributes. <whitequark>
    * d5ac858 - build/lattice/diamond: save LDF project after creating it. <whitequark>
    * 2025071 - build/lattice/diamond: shorten pointlessly long paths. <whitequark>
    * 7303a8a - build/platforms/versaecp55g: add PCIe pins. <whitequark>
    * 0c5d42c - Add Project Trellis Backend (#156) <William D. Jones>
    * 37deff1 - build/platforms/versaecp55g: fix IOStandard for ext_clk. <whitequark>
    * c79d988 - build/platforms/versaecp55g: add X3 external connector. <whitequark>
    * d60cea0 - build/platforms/versaecp55g: add external clock input. <whitequark>
    * c51a064 - build/platforms/versaecp55g: allow programming without ispCLOCK in chain. <whitequark>
    * 34eeb3b - build/platforms/versaecp55g: import from litex. <whitequark>
    * 7bdc4ed - build/lattice/diamond: add Linux support. <whitequark>
    * 3a84a8b - build/lattice/diamond: only run Jedecgen for MachXO. <whitequark>
    * 966781b - class Tristate: add support for target parameter with oe, o and i subsignals. (#148) <Staf Verhaegen>
    * 907afd5 - platforms/icebreaker: Rename I/O w/ @esden's feedback. <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 30d9a3e2c22459470605b8d46f27d339b47f7987 litedram (remotes/origin/HEAD)
 52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
 48f662e3928aa5af25aef932a8b1744d1f29c260 litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 bc173380f21f82a82fc41e9face61b0c33e7f8e4 litex (v0.1-602-gbc173380)
 c285c12905cca3d8db59ce9fba3bbcd7e781e3c3 migen (0.6.dev-209-gc285c12)
    @mithro
    mithro committed Nov 14, 2018
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  2. Merge pull request #102 from mithro/update 

    Updating submodules.
    @mithro
    mithro committed Nov 14, 2018
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