whitequark · Nov 18, 2018 · Nov 18, 2018 · Nov 18, 2018
diff --git a/.travis.yml b/.travis.yml
@@ -13,9 +13,3 @@ install:
 script:
   - "(cd software && python setup.py install)"
   - "(cd software && python setup.py test)"
-notifications:
-  irc:
-    channels:
-      - "chat.freenode.net##openfpga"
-    use_notice: true
-    skip_join: true
diff --git a/software/glasgow/applet/__init__.py b/software/glasgow/applet/__init__.py
@@ -159,6 +159,7 @@ def wrapper(self):
 from .i2c.tps6598x import I2CTPS6598xApplet
 from .jtag import JTAGApplet
 from .jtag.arc import JTAGARCApplet
+from .jtag.mec1618 import JTAGMEC1618Applet
 from .jtag.mips import JTAGMIPSApplet
 from .jtag.pinout import JTAGPinoutApplet
 from .jtag.svf import JTAGSVFApplet

diff --git a/software/glasgow/applet/jtag/arc.py b/software/glasgow/applet/jtag/arc.py
@@ -3,13 +3,12 @@
 
 import logging
 import argparse
-import struct
 
 from . import JTAGApplet
 from .. import *
 from ...pyrepl import *
 from ...arch.jtag import *
-from ...arch.arc.jtag import *
+from ...arch.arc import *
 from ...database.arc import *
 
 
@@ -51,7 +50,7 @@ async def read(self, address, space):
         else:
             assert False
 
-        self._log("read space=%s address=%08x", space, address)
+        self._log("read %s address=%08x", space, address)
         dr_address = DR_ADDRESS(Address=address)
         await self.lower.write_ir(IR_ADDRESS)
         await self.lower.write_dr(dr_address.to_bitarray())
@@ -74,7 +73,7 @@ async def write(self, address, data, space):
         else:
             assert False
 
-        self._log("write space=%s address=%08x data=%08x", space, address, data)
+        self._log("write %s address=%08x data=%08x", space, address, data)
         dr_address = DR_ADDRESS(Address=address)
         await self.lower.write_ir(IR_ADDRESS)
         await self.lower.write_dr(dr_address.to_bitarray())
@@ -85,9 +84,11 @@ async def write(self, address, data, space):
         await self.lower.write_dr(dr_txn_command)
         await self._wait_txn()
 
+    async def set_halted(self, halted):
+        await self.write(AUX_STATUS32_addr, AUX_STATUS32(halted=halted).to_int(), space="aux")
+
 
 class JTAGARCApplet(JTAGApplet, name="jtag-arc"):
-    preview = True
     logger = logging.getLogger(__name__)
     help = "debug ARC processors via JTAG"
     description = """

diff --git a/software/glasgow/applet/jtag/mec1618.py b/software/glasgow/applet/jtag/mec1618.py
@@ -0,0 +1,74 @@
+# Ref: Microchip MEC1618/MEC1618i Low Power 32-bit Microcontroller with Embedded Flash
+# Document Number: DS00002339A
+
+import logging
+import argparse
+import struct
+
+from .arc import JTAGARCApplet
+from .. import *
+from ...support.aobject import *
+from ...pyrepl import *
+from ...arch.arc import *
+
+
+FIRMWARE_SIZE = 0x30_000
+
+
+class JTAGMEC1618Interface(aobject):
+    async def __init__(self, interface, logger):
+        self.lower   = interface
+        self._logger = logger
+        self._level  = logging.DEBUG if self._logger.name == __name__ else logging.TRACE
+
+        idcode, device = await self.lower.identify()
+        if device is None or device.name != "ARC6xx":
+            raise GlasgowAppletError("cannot operate on unknown device IDCODE=%08x"
+                                     % idcode.to_int())
+
+        self._log("halting CPU")
+        await self.lower.set_halted(True)
+
+    def _log(self, message, *args):
+        self._logger.log(self._level, "MEC1618: " + message, *args)
+
+    async def read_firmware(self):
+        words = []
+        for offset in range(0, FIRMWARE_SIZE, 4):
+            self._log("read firmware offset=%05x", offset)
+            words.append(await self.lower.read(offset, space="memory"))
+        return words
+
+
+class JTAGMEC1618Applet(JTAGARCApplet, name="jtag-mec1618"):
+    preview = True
+    logger = logging.getLogger(__name__)
+    help = "debug Microchip MEC1618 embedded controller via JTAG"
+    description = """
+    Debug Microchip MEC1618/MEC1618i embedded controller via the JTAG interface.
+    """
+
+    async def run(self, device, args):
+        arc_iface = await super().run(device, args)
+        return await JTAGMEC1618Interface(arc_iface, self.logger)
+
+    @classmethod
+    def add_interact_arguments(cls, parser):
+        p_operation = parser.add_subparsers(dest="operation", metavar="OPERATION")
+
+        p_read_firmware = p_operation.add_parser(
+            "read-firmware", help="read EC firmware")
+        p_read_firmware.add_argument(
+            "file", metavar="FILE", type=argparse.FileType("wb"),
+            help="write EC firmware to FILE")
+
+        p_repl = p_operation.add_parser(
+            "repl", help="drop into Python shell; use `mec_iface` to communicate")
+
+    async def interact(self, device, args, mec_iface):
+        if args.operation == "read-firmware":
+            for word in await mec_iface.read_firmware():
+                args.file.write(struct.pack("<L", word))
+
+        if args.operation == "repl":
+            await AsyncInteractiveConsole(locals={"mec_iface":mec_iface}).interact()
diff --git a/software/glasgow/arch/arc/__init__.py b/software/glasgow/arch/arc/__init__.py
@@ -0,0 +1,2 @@
+from .core import *
+from .jtag import *
diff --git a/software/glasgow/arch/arc/core.py b/software/glasgow/arch/arc/core.py
@@ -0,0 +1,61 @@
+# Ref: https://sourceware.org/binutils/docs/as/ARC_002dRegs.html
+# Ref: linux/arch/arc/include/asm/arcregs.h
+
+from ...support.bits import *
+
+
+__all__ = [
+    # Core AUX registers
+    "AUX_IDENTITY_addr", "AUX_PC_addr", "AUX_STATUS32_addr", "AUX_STATUS32_P0_addr",
+    "AUX_AUX_USER_SP_addr", "AUX_INT_VECTOR_BASE_addr",
+    "AUX_STATUS32",
+    # Build configuration AUX registers
+    "AUX_DCCMBASE_BCR_addr", "AUX_CRC_BCR_addr", "AUX_DVFB_BCR_addr", "AUX_EXTARITH_BCR_addr",
+    "AUX_VECBASE_BCR_addr", "AUX_PERIBASE_BCR_addr", "AUX_D_UNCACH_BCR_addr", "AUX_FP_BCR_addr",
+    "AUX_DPFP_BCR_addr", "AUX_MMU_BCR_addr", "AUX_DCCM_BCR_addr", "AUX_TIMERS_BCR_addr",
+    "AUX_ICCM_BCR_addr", "AUX_XY_MEM_BCR_addr", "AUX_MAC_BCR_addr", "AUX_MUL_BCR_addr",
+    "AUX_SWAP_BCR_addr", "AUX_NORM_BCR_addr", "AUX_MIXMAX_BCR_addr", "AUX_BARREL_BCR_addr",
+]
+
+
+AUX_IDENTITY_addr            = 0x04
+AUX_PC_addr                  = 0x06
+AUX_STATUS32_addr            = 0x0a
+AUX_STATUS32_P0_addr         = 0x0b
+AUX_AUX_USER_SP_addr         = 0x0d
+AUX_INT_VECTOR_BASE_addr     = 0x25
+
+AUX_STATUS32 = Bitfield("AUX_STATUS32", 4, [
+    ("H",   1),
+    ("E1",  1),
+    ("E2",  1),
+    ("A1",  1),
+    ("A2",  1),
+    ("AE",  1),
+    ("DE",  1),
+    ("U",   1),
+    (None,  4),
+    ("L",   1),
+])
+
+# Build Configuration Registers
+AUX_DCCMBASE_BCR_addr        = 0x61
+AUX_CRC_BCR_addr             = 0x62
+AUX_DVFB_BCR_addr            = 0x64
+AUX_EXTARITH_BCR_addr        = 0x65
+AUX_VECBASE_BCR_addr         = 0x68
+AUX_PERIBASE_BCR_addr        = 0x69
+AUX_D_UNCACH_BCR_addr        = 0x6a
+AUX_FP_BCR_addr              = 0x6b
+AUX_DPFP_BCR_addr            = 0x6c
+AUX_MMU_BCR_addr             = 0x6f
+AUX_DCCM_BCR_addr            = 0x74
+AUX_TIMERS_BCR_addr          = 0x75
+AUX_ICCM_BCR_addr            = 0x78
+AUX_XY_MEM_BCR_addr          = 0x79
+AUX_MAC_BCR_addr             = 0x7a
+AUX_MUL_BCR_addr             = 0x7b
+AUX_SWAP_BCR_addr            = 0x7c
+AUX_NORM_BCR_addr            = 0x7d
+AUX_MIXMAX_BCR_addr          = 0x7e
+AUX_BARREL_BCR_addr          = 0x7f