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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 3b23645fb7ef
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Dec 14, 2018

  1. fhdl.ast: fix Switch with constant test.

    whitequark committed Dec 14, 2018
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    50ba443 View commit details
  2. genlib.io: import TSTriple from Migen.

    whitequark committed Dec 14, 2018
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    7200346 View commit details
  3. compat: add fhdl.specials.TSTriple shim.

    whitequark committed Dec 14, 2018
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    3b23645 View commit details
Showing with 56 additions and 3 deletions.
  1. +1 −1 nmigen/compat/__init__.py
  2. +18 −0 nmigen/compat/fhdl/specials.py
  3. +2 −2 nmigen/fhdl/ast.py
  4. +21 −0 nmigen/genlib/io.py
  5. +14 −0 nmigen/test/test_fhdl_dsl.py
2 changes: 1 addition & 1 deletion nmigen/compat/__init__.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from .fhdl.structure import *
from .fhdl.module import *
# from .fhdl.specials import *
from .fhdl.specials import *
from .fhdl.bitcontainer import *
# from .fhdl.decorators import *
# from .fhdl.simplify import *
18 changes: 18 additions & 0 deletions nmigen/compat/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
from ...genlib.io import TSTriple as NewTSTriple


__all__ = ["TSTriple"]


class CompatTSTriple(NewTSTriple):
def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
name=None):
super().__init__(shape=bits_sign, min=min, max=max,
reset_o=reset_o, reset_oe=reset_oe, reset_i=reset_i,
name=name)

def get_tristate(self, target):
raise NotImplementedError("TODO")


TSTriple = CompatTSTriple
4 changes: 2 additions & 2 deletions nmigen/fhdl/ast.py
Original file line number Diff line number Diff line change
@@ -678,9 +678,9 @@ def __init__(self, test, cases):
self.cases = OrderedDict()
for key, stmts in cases.items():
if isinstance(key, (bool, int)):
key = "{:0{}b}".format(key, len(test))
key = "{:0{}b}".format(key, len(self.test))
elif isinstance(key, str):
assert len(key) == len(test)
assert len(key) == len(self.test)
else:
raise TypeError
if not isinstance(stmts, Iterable):
21 changes: 21 additions & 0 deletions nmigen/genlib/io.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
from ..fhdl import *


__all__ = ["TSTriple"]


class TSTriple:
def __init__(self, shape=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
name=None):
self.o = Signal(shape, min=min, max=max, reset=reset_o,
name=None if name is None else name + "_o")
self.oe = Signal(reset=reset_oe,
name=None if name is None else name + "_oe")
self.i = Signal(shape, min=min, max=max, reset=reset_i,
name=None if name is None else name + "_i")

def __len__(self):
return len(self.o)

def get_fragment(self, platform):
return Fragment()
14 changes: 14 additions & 0 deletions nmigen/test/test_fhdl_dsl.py
Original file line number Diff line number Diff line change
@@ -263,6 +263,20 @@ def test_Switch_default(self):
)
""")

def test_Switch_const_test(self):
m = Module()
with m.Switch(1):
with m.Case(1):
m.d.comb += self.c1.eq(1)
m._flush()
self.assertRepr(m._statements, """
(
(switch (const 1'd1)
(case 1 (eq (sig c1) (const 1'd1)))
)
)
""")

def test_Case_width_wrong(self):
m = Module()
with m.Switch(self.w1):