Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 1f10bd96b92f
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: cc96a7ecfa16
Choose a head ref
  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 15, 2018

  1. doc: update COMPAT_SUMMARY to reflect actual status.

    whitequark committed Dec 15, 2018
    Copy the full SHA
    cc96a7e View commit details
Showing with 159 additions and 162 deletions.
  1. +159 −162 doc/COMPAT_SUMMARY.md
321 changes: 159 additions & 162 deletions doc/COMPAT_SUMMARY.md
Original file line number Diff line number Diff line change
@@ -19,172 +19,169 @@ API change legend:
When describing renames or replacements, `mod` refers to a 3rd-party package `mod` (no nMigen implementation provided), `.mod.item` refers to `nmigen.mod.item`, and "(import `.item`)" means that, while `item` is provided under `nmigen.mod.item`, it is aliased to, and should be imported from a shorter path for readability.

Status legend:
- (×) Intended replacement (the API is decided on)
- () Implemented replacement (the API and compatibility shim are provided)
- (+) Verified replacement and/or compatibility shim (the compatibility shim is manually reviewed and has 100% coverage)
- () No direct replacement or compatibility shim is provided
- (−) No decision yet, or no replacement implemented
- (+) Implemented replacement (the API and/or compatibility shim are provided)
- () Verified replacement and/or compatibility shim (the compatibility shim is manually reviewed and/or has 100% test coverage)
- () No direct replacement or compatibility shim is provided

Compatibility summary
---------------------

- (×) `fhdl`
- (×) `bitcontainer``.tools`
- (×) `log2_int` id
- (×) `bits_for` id
- (×) `value_bits_sign``Value.shape`
- (×) `conv_output` ?
- (×) `decorators``.fhdl.xfrm`
- () `fhdl`
- (+) `bitcontainer``.tools`
- (+) `log2_int` id
- (+) `bits_for` id
- (+) `value_bits_sign``Value.shape`
- () `conv_output` ?
- (+) `decorators``.fhdl.xfrm`
Note: `transform_*` methods not considered part of public API.
- () `ModuleTransformer` **brk**
- () `ControlInserter` **brk**
- (×) `CEInserter` id, `clock_domains=``controls=`
- (×) `ResetInserter` id, `clock_domains=``controls=`
- (×) `ClockDomainsRenamer``DomainRenamer`, `cd_remapping=``domain_map=`
- () `edif` **brk**
- (×) `module` **obs**`.fhdl.dsl`
- (×) `FinalizeError` **obs**
- (×) `Module` **obs**`.fhdl.dsl.Module`
- () `namer` **brk**
- (×) `simplify` ?
- (×) `FullMemoryWE` ?
- (×) `MemoryToArray` ?
- (×) `SplitMemory` ?
- (×) `specials` **obs**
- (×) `Special` ?
- (×) `Tristate` ?
- (×) `TSTriple``.genlib.io.TSTriple`, `bits_sign=``shape=`
- (×) `Instance` ?
- (×) `READ_FIRST`/`WRITE_FIRST`/`NO_CHANGE` ?
- (×) `_MemoryPort` ?
- (×) `Memory` ?
- (×) `structure``.fhdl.ast`
- (×) `DUID` id
- (×) `_Value``Value`
- () `ModuleTransformer` **brk**
- () `ControlInserter` **brk**
- (+) `CEInserter` id, `clock_domains=``controls=`
- (+) `ResetInserter` id, `clock_domains=``controls=`
- (+) `ClockDomainsRenamer``DomainRenamer`, `cd_remapping=``domain_map=`
- () `edif` **brk**
- (+) `module` **obs**`.fhdl.dsl`
- (+) `FinalizeError` **obs**
- (+) `Module` **obs**`.fhdl.dsl.Module`
- () `namer` **brk**
- () `simplify` ?
- () `FullMemoryWE` ?
- () `MemoryToArray` ?
- () `SplitMemory` ?
- () `specials` **obs**
- () `Special` ?
- () `Tristate` ?
- (+) `TSTriple``.genlib.io.TSTriple`, `bits_sign=``shape=`
- () `Instance` ?
- () `READ_FIRST`/`WRITE_FIRST`/`NO_CHANGE` ?
- () `_MemoryPort` ?
- () `Memory` ?
- () `structure``.fhdl.ast`
- (+) `DUID` id
- (+) `_Value``Value`
Note: values no longer valid as keys in `dict` and `set`; use `ValueDict` and `ValueSet` instead.
- (×) `wrap``Value.wrap`
- (×) `_Operator``Operator`
- (×) `Mux``Mux`
- (×) `_Slice``Slice`, `stop=``end=`, `.stop``.end`
- (×) `_Part``Part`
- (×) `Cat` id, `.l``.operands`
- (×) `Replicate``Repl`, `v=``value=`, `n=``count=`, `.v``.value`, `.n``.count`
- (×) `Constant``Const`, `bits_sign=``shape=`
- (×) `Signal` id, `bits_sign=``shape=`, `attr=``attrs=`, `name_override=`∼, `related=`, `variable=`
- (×) `ClockSignal` id, `cd=``domain=`
- (×) `ResetSignal` id, `cd=``domain=`
- (×) `_Statement``Statement`
- (×) `_Assign``Assign`, `l=``lhs=`, `r=``rhs=`
- (×) `_check_statement` **obs**`Statement.wrap`
- (×) `If` **obs**`.fhdl.dsl.Module.If`
- (×) `Case` **obs**`.fhdl.dsl.Module.Switch`
- (×) `_ArrayProxy` ?
- (×) `Array` ?
- (×) `ClockDomain``.fhdl.cd.ClockDomain`
- (×) `_ClockDomainList` ?
- (×) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` ?
- (∼) `_Fragment` **brk**`.fhdl.ir.Fragment`
- (×) `tools` **brk**
- (×) `list_signals` ?
- (×) `list_targets` ?
- (×) `list_inputs` ?
- (×) `group_by_targets` ?
- (∼) `list_special_ios` **brk**
- (∼) `list_clock_domains_expr` **brk**
- (×) `list_clock_domains` ?
- (×) `is_variable` ?
- (∼) `generate_reset` **brk**
- (∼) `insert_reset` **brk**
- (∼) `insert_resets` **brk**`.fhdl.xfrm.ResetInserter`
- (∼) `lower_basics` **brk**
- (∼) `lower_complex_slices` **brk**
- (∼) `lower_complex_parts` **brk**
- (∼) `rename_clock_domain_expr` **brk**
- (∼) `rename_clock_domain` **brk**`.fhdl.xfrm.DomainRenamer`
- (∼) `call_special_classmethod` **brk**
- (∼) `lower_specials` **brk**
- (×) `tracer` **brk**
- (×) `get_var_name` ?
- (×) `remove_underscore` ?
- (×) `get_obj_var_name` ?
- (×) `index_id` ?
- (×) `trace_back` ?
- (×) `verilog`
- (×) `DummyAttrTranslate` ?
- (×) `convert` **obs**`.back.verilog.convert`
- (∼) `visit` **brk**`.fhdl.xfrm`
- (∼) `NodeVisitor` **brk**
- (∼) `NodeTransformer` **brk**`.fhdl.xfrm.ValueTransformer`/`.fhdl.xfrm.StatementTransformer`
- (×) `genlib`
- (×) `cdc` ?
- (×) `MultiRegImpl` ?
- (×) `MultiReg` id
- (×) `PulseSynchronizer` ?
- (×) `BusSynchronizer` ?
- (×) `GrayCounter` ?
- (×) `GrayDecoder` ?
- (×) `ElasticBuffer` ?
- (×) `lcm` ?
- (×) `Gearbox` ?
- (×) `coding` ?
- (×) `Encoder` ?
- (×) `PriorityEncoder` ?
- (×) `Decoder` ?
- (×) `PriorityDecoder` ?
- (×) `divider` ?
- (×) `Divider`
- (×) `fifo` ?
- (×) `SyncFIFO` ?
- (×) `SyncFIFOBuffered` ?
- (×) `AsyncFIFO` ?
- (×) `AsyncFIFOBuffered` ?
- (×) `_FIFOInterface` ?
- (×) `fsm` **obs**
- (×) `AnonymousState` **obs**
- (×) `NextState` **obs**
- (×) `NextValue` **obs**
- (×) `_LowerNext` **obs**
- (×) `FSM` **obs**
- (×) `io` ?
- (×) `DifferentialInput` ?
- (×) `DifferentialOutput` ?
- (×) `CRG` ?
- (×) `DDRInput` ?
- (×) `DDROutput` ?
- (×) `misc` ?
- (×) `split` ?
- (×) `displacer` ?
- (×) `chooser` ?
- (×) `timeline` ?
- (×) `WaitTimer` ?
- (×) `BitSlip` ?
- (×) `record` ?
- (×) `DIR_NONE` ?
- (×) `DIR_S_TO_M` ?
- (×) `DIR_M_TO_S` ?
- (×) `set_layout_parameters` ?
- (×) `layout_len` ?
- (×) `layout_get` ?
- (×) `layout_partial` ?
- (×) `Record` ?
- (×) `resetsync` ?
- (×) `AsyncResetSynchronizer` ?
- (×) `roundrobin` ?
- (×) `SP_WITHDRAW` ?
- (×) `SP_CE` ?
- (×) `RoundRobin` ?
- (×) `sort` ?
- (×) `BitonicSort` ?
- (×) `sim` **obs**`.back.pysim`
- (∼) `core` **brk**
- (∼) `vcd` **brk**`vcd`
- (+) `wrap``Value.wrap`
- (+) `_Operator``Operator`
- (+) `Mux``Mux`
- (+) `_Slice``Slice`, `stop=``end=`, `.stop``.end`
- (+) `_Part``Part`
- (+) `Cat` id, `.l``.operands`
- (+) `Replicate``Repl`, `v=``value=`, `n=``count=`, `.v``.value`, `.n``.count`
- (+) `Constant``Const`, `bits_sign=``shape=`
- (+) `Signal` id, `bits_sign=``shape=`, `attr=``attrs=`, `name_override=`∼, `related=`, `variable=`
- (+) `ClockSignal` id, `cd=``domain=`
- (+) `ResetSignal` id, `cd=``domain=`
- (+) `_Statement``Statement`
- (+) `_Assign``Assign`, `l=``lhs=`, `r=``rhs=`
- (-) `_check_statement` **obs**`Statement.wrap`
- (+) `If` **obs**`.fhdl.dsl.Module.If`
- (+) `Case` **obs**`.fhdl.dsl.Module.Switch`
- (−) `_ArrayProxy` ?
- (−) `Array` ?
- (+) `ClockDomain``.fhdl.cd.ClockDomain`
- (−) `_ClockDomainList` ?
- (−) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` ?
- (⊙) `_Fragment` **brk**`.fhdl.ir.Fragment`
- (−) `tools` **brk**
- (−) `list_signals` ?
- (−) `list_targets` ?
- (−) `list_inputs` ?
- (−) `group_by_targets` ?
- (⊙) `list_special_ios` **brk**
- (⊙) `list_clock_domains_expr` **brk**
- (−) `list_clock_domains` ?
- (−) `is_variable` ?
- (⊙) `generate_reset` **brk**
- (⊙) `insert_reset` **brk**
- (⊙) `insert_resets` **brk**`.fhdl.xfrm.ResetInserter`
- (⊙) `lower_basics` **brk**
- (⊙) `lower_complex_slices` **brk**
- (⊙) `lower_complex_parts` **brk**
- (⊙) `rename_clock_domain_expr` **brk**
- (⊙) `rename_clock_domain` **brk**`.fhdl.xfrm.DomainRenamer`
- (⊙) `call_special_classmethod` **brk**
- (⊙) `lower_specials` **brk**
- (−) `tracer` **brk**
- (−) `get_var_name` ?
- (−) `remove_underscore` ?
- (−) `get_obj_var_name` ?
- (−) `index_id` ?
- (−) `trace_back` ?
- (−) `verilog`
- (−) `DummyAttrTranslate` ?
- (−) `convert` **obs**`.back.verilog.convert`
- (⊙) `visit` **brk**`.fhdl.xfrm`
- (⊙) `NodeVisitor` **brk**
- (⊙) `NodeTransformer` **brk**`.fhdl.xfrm.ValueTransformer`/`.fhdl.xfrm.StatementTransformer`
- (−) `genlib`
- (−) `cdc` ?
- (−) `MultiRegImpl` ?
- (+) `MultiReg` id
- (−) `PulseSynchronizer` ?
- (−) `BusSynchronizer` ?
- (−) `GrayCounter` ?
- (−) `GrayDecoder` ?
- (−) `ElasticBuffer` ?
- (−) `lcm` ?
- (−) `Gearbox` ?
- (−) `coding` ?
- (−) `Encoder` ?
- (−) `PriorityEncoder` ?
- (−) `Decoder` ?
- (−) `PriorityDecoder` ?
- (−) `divider` ?
- (−) `Divider` ?
- (−) `fifo` ?
- (−) `SyncFIFO` ?
- (−) `SyncFIFOBuffered` ?
- (−) `AsyncFIFO` ?
- (−) `AsyncFIFOBuffered` ?
- (−) `_FIFOInterface` ?
- (+) `fsm` **obs**
- (+) `AnonymousState` **obs**
- (+) `NextState` **obs**
- (+) `NextValue` **obs**
- (+) `_LowerNext` **obs**
- (+) `FSM` **obs**
- (−) `io` ?
- (−) `DifferentialInput` ?
- (−) `DifferentialOutput` ?
- (−) `CRG` ?
- (−) `DDRInput` ?
- (−) `DDROutput` ?
- (−) `misc` ?
- (−) `split` ?
- (−) `displacer` ?
- (−) `chooser` ?
- (−) `timeline` ?
- (−) `WaitTimer` ?
- (−) `BitSlip` ?
- (−) `record` ?
- (−) `DIR_NONE`/`DIR_S_TO_M`/`DIR_M_TO_S` ?
- (−) `set_layout_parameters` ?
- (−) `layout_len` ?
- (−) `layout_get` ?
- (−) `layout_partial` ?
- (−) `Record` ?
- (−) `resetsync` ?
- (−) `AsyncResetSynchronizer` ?
- (−) `roundrobin` ?
- (−) `SP_WITHDRAW`/`SP_CE` ?
- (−) `RoundRobin` ?
- (−) `sort` ?
- (−) `BitonicSort` ?
- (-) `sim` **obs**`.back.pysim`
- (⊙) `core` **brk**
- (⊙) `vcd` **brk**`vcd`
Note: only items directly under `nmigen.compat.sim`, not submodules, are provided.
- (×) `Simulator` **brk**
- (×) `run_simulation` **obs**`.back.pysim.Simulator`
- (×) `passive` **obs**`.fhdl.ast.Passive`
- (×) `build` ?
- (×) `util` **obs**
- (×) `misc``.tools`
- (×) `flat_iteration``.flatten`
- () `xdir` **brk**
- () `gcd_multiple` **brk**
- () `treeviz` **brk**
- () `Simulator` **brk**
- (+) `run_simulation` **obs**`.back.pysim.Simulator`
- () `passive` **obs**`.fhdl.ast.Passive`
- () `build` ?
- (+) `util` **obs**
- (+) `misc``.tools`
- (+) `flat_iteration``.flatten`
- () `xdir` **brk**
- () `gcd_multiple` **brk**
- () `treeviz` **brk**