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base repository: whitequark/glasgow
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head repository: whitequark/glasgow
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compare: 9f617b2e8c58
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  • 3 commits
  • 7 files changed
  • 1 contributor

Commits on Dec 15, 2018

  1. gateware, applet: more imports cleanup. NFC.

    @whitequark
    whitequark committed Dec 15, 2018
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    1c5d1be View commit details

  2. gateware.uart: simplify. NFC.

    @whitequark
    whitequark committed Dec 15, 2018
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    1e00822 View commit details

  3. gateware.uart: start porting to nMigen.

    @whitequark
    whitequark committed Dec 15, 2018
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    9f617b2 View commit details
1 change: 0 additions & 1 deletion software/glasgow/applet/jtag/__init__.py
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Original file line number Diff line number Diff line change
@@ -4,7 +4,6 @@
from bitarray import bitarray
from migen import *
from migen.genlib.cdc import MultiReg
from migen.genlib.fsm import FSM

from .. import *
from ...support.pyrepl import *
1 change: 0 additions & 1 deletion software/glasgow/applet/jtag_pinout/__init__.py
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@@ -3,7 +3,6 @@
import random
from functools import reduce
from migen import *
from migen.genlib.fsm import FSM
from migen.genlib.cdc import MultiReg

from .. import *
1 change: 0 additions & 1 deletion software/glasgow/applet/nand_flash/__init__.py
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@@ -4,7 +4,6 @@
import struct
from migen import *
from migen.genlib.cdc import MultiReg
from migen.genlib.fsm import FSM

from .. import *
from ...database.jedec import *
1 change: 0 additions & 1 deletion software/glasgow/applet/shugart_floppy/__init__.py
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@@ -300,7 +300,6 @@
import crcmod
import math
from migen import *
from migen.genlib.fsm import FSM
from migen.genlib.cdc import MultiReg

from .. import *
6 changes: 5 additions & 1 deletion software/glasgow/gateware/__init__.py
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@@ -1,5 +1,9 @@
import functools
from migen import *
import os
if os.getenv("NMIGEN"):
from nmigen.compat import run_simulation
else:
from migen import run_simulation


__all__ = ["GatewareBuildError", "simulation_test"]
1 change: 0 additions & 1 deletion software/glasgow/gateware/analyzer.py
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@@ -3,7 +3,6 @@
from migen import *
from migen.genlib.fifo import _FIFOInterface, SyncFIFOBuffered
from migen.genlib.coding import PriorityEncoder, PriorityDecoder
from migen.genlib.fsm import FSM


__all__ = ["EventSource", "EventAnalyzer", "TraceDecodingError", "TraceDecoder"]
12 changes: 8 additions & 4 deletions software/glasgow/gateware/uart.py
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Original file line number Diff line number Diff line change
@@ -1,5 +1,10 @@
from migen import *
from migen.genlib.cdc import MultiReg
import os
if os.getenv("NMIGEN"):
from nmigen.compat import *
from nmigen.compat.genlib.cdc import MultiReg
else:
from migen import *
from migen.genlib.cdc import MultiReg


__all__ = ['UART', 'uart_bit_cyc']
@@ -299,8 +304,7 @@ def calc_parity(sig, kind):

class UARTTestbench(Module):
def __init__(self):
self.rx_t = TSTriple()
self.rx_t.i = Signal(reset=1)
self.rx_t = TSTriple(reset_i=1)
self.rx_i = self.rx_t.i

self.tx_t = TSTriple()