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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: e230383aac6d
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 14, 2018

  1. compat.sim: match clock period.

    whitequark committed Dec 14, 2018
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    0ef5ced View commit details
  2. back.pysim: make initial phase configurable.

    whitequark committed Dec 14, 2018
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    e230383 View commit details
Showing with 6 additions and 4 deletions.
  1. +4 −2 nmigen/back/pysim.py
  2. +2 −2 nmigen/compat/sim/__init__.py
6 changes: 4 additions & 2 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -250,15 +250,17 @@ def sync_process():
pass
self.add_process(sync_process())

def add_clock(self, period, domain="sync"):
def add_clock(self, period, phase=None, domain="sync"):
if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period

half_period = period / 2
if phase is None:
phase = half_period
clk = self._domains[domain].clk
def clk_process():
yield Passive()
yield Delay(half_period)
yield Delay(phase)
while True:
yield clk.eq(1)
yield Delay(half_period)
4 changes: 2 additions & 2 deletions nmigen/compat/sim/__init__.py
Original file line number Diff line number Diff line change
@@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name

with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
for domain, period in clocks.items():
sim.add_clock(period, domain)
sim.add_clock(period / 1e9, domain=domain)
for domain, process in generators.items():
sim.add_sync_process(process, domain)
sim.add_sync_process(process, domain=domain)
sim.run()