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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 0015713bfb06
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 14, 2018

  1. back.pysim: simplify.

    whitequark committed Dec 14, 2018
    Copy the full SHA
    a6a8703 View commit details
  2. Copy the full SHA
    0015713 View commit details
Showing with 22 additions and 20 deletions.
  1. +22 −20 nmigen/back/pysim.py
42 changes: 22 additions & 20 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -33,11 +33,11 @@ def set(self, signal, value):

def commit(self, signal):
old_value = self.curr[signal]
if self.curr[signal] != self.next[signal]:
new_value = self.next[signal]
if old_value != new_value:
self.next_dirty.remove(signal)
self.curr_dirty.add(signal)
self.curr[signal] = self.next[signal]
new_value = self.curr[signal]
self.curr[signal] = new_value
return old_value, new_value


@@ -204,6 +204,7 @@ def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):

self._started = False
self._timestamp = 0.
self._delta = 0.
self._epsilon = 1e-10
self._fastest_clock = self._epsilon
self._state = _State()
@@ -288,7 +289,7 @@ def add_fragment(fragment, scope=()):
add_fragment(subfragment, (*scope, name))
add_fragment(root_fragment)

for fragment, fragment_name in hierarchy.items():
for fragment, fragment_scope in hierarchy.items():
for signal in fragment.iter_signals():
self._signals.add(signal)

@@ -326,10 +327,10 @@ def add_fragment(fragment, scope=()):
else:
var_name_suffix = "{}${}".format(var_name, suffix)
self._vcd_signals[signal].add(self._vcd_writer.register_var(
scope=".".join(fragment_name), name=var_name_suffix,
scope=".".join(fragment_scope), name=var_name_suffix,
var_type=var_type, size=var_size, init=var_init))
if signal not in self._vcd_names:
self._vcd_names[signal] = ".".join(fragment_name + (var_name_suffix,))
self._vcd_names[signal] = ".".join(fragment_scope + (var_name_suffix,))
break
except KeyError:
suffix = (suffix or 0) + 1
@@ -401,14 +402,15 @@ def _commit_signal(self, signal, domains):
var_value = signal.decoder(new).replace(" ", "_")
else:
var_value = new
self._vcd_writer.change(vcd_signal, self._timestamp / self._epsilon, var_value)
vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
self._vcd_writer.change(vcd_signal, vcd_timestamp, var_value)

def _commit_comb_signals(self, domains):
"""Perform the comb part of IR processes (aka RTLIL always)."""
# Take the computed value (at the start of this delta cycle) of every comb signal and
# update the value for this delta cycle.
for signal in self._state.next_dirty:
if signal in self._comb_signals or signal in self._user_signals:
if signal in self._comb_signals:
self._commit_signal(signal, domains)

def _commit_sync_signals(self, domains):
@@ -417,7 +419,7 @@ def _commit_sync_signals(self, domains):
while domains:
# Advance the timeline a bit (purely for observational purposes) and commit all of them
# at the same timestamp.
self._timestamp += self._epsilon
self._delta += self._epsilon
curr_domains, domains = domains, set()

while curr_domains:
@@ -505,24 +507,22 @@ def format_process(process):
process.throw(e)

def step(self, run_passive=False):
deadline = None
if self._wait_deadline:
# Are there any delta cycles we should run?
if self._state.curr_dirty:
# We might run some delta cycles, and we have simulator processes waiting on
# a deadline. Take care to not exceed the closest deadline.
deadline = min(self._wait_deadline.values())

# Are there any delta cycles we should run?
while self._state.curr_dirty:
self._timestamp += self._epsilon
if deadline is not None and self._timestamp >= deadline:
if self._wait_deadline and \
(self._timestamp + self._delta) >= min(self._wait_deadline.values()):
# Oops, we blew the deadline. We *could* run the processes now, but this is
# virtually certainly a logic loop and a design bug, so bail out instead.d
raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")

domains = set()
self._update_dirty_signals()
self._commit_comb_signals(domains)
while self._state.curr_dirty:
self._update_dirty_signals()
self._commit_comb_signals(domains)
self._commit_sync_signals(domains)
return True

# Are there any processes that haven't had a chance to run yet?
if len(self._processes) > len(self._suspended):
@@ -540,6 +540,7 @@ def step(self, run_passive=False):
del self._wait_deadline[process]
self._suspended.remove(process)
self._timestamp = deadline
self._delta = 0.
self._run_process(process)
return True

@@ -559,7 +560,8 @@ def run_until(self, deadline, run_passive=False):

def __exit__(self, *args):
if self._vcd_writer:
self._vcd_writer.close(self._timestamp / self._epsilon)
vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
self._vcd_writer.close(vcd_timestamp)

if self._vcd_file and self._gtkw_file:
gtkw_save = GTKWSave(self._gtkw_file)