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base repository: whitequark/glasgow
base: 226f6cbda20e
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head repository: whitequark/glasgow
compare: 9080eaf696b1
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  • 5 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 4, 2018

  1. revC: update incorrect comment re: Vbus threshold

    @marcan
    marcan committed Dec 4, 2018
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  2. revC: connect Port A 4,6 to extra FPGA I/Os as well as GBUFs 

    This allows flexibility in using the PLL with or without the pins as
clock inputs.
    @marcan
    marcan committed Dec 4, 2018
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  3. revC: schematic style fix (add wire for net label)

    @marcan
    marcan committed Dec 4, 2018
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  4. revC: remove additional I/O port silkscreen markings

    @marcan
    marcan committed Dec 4, 2018
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  5. revC: move USB D+ closer to D- near U15

    @marcan
    marcan committed Dec 4, 2018
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