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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 20a04bca882f
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  • 3 commits
  • 6 files changed
  • 1 contributor

Commits on Dec 15, 2018

  1. doc: update COMPAT_SUMMARY.

    whitequark committed Dec 15, 2018
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    6c601fe View commit details
  2. examples: rename clkdiv/ctrl to ctr/ctr_ce.

    whitequark committed Dec 15, 2018
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    1adf58f View commit details
  3. back.pysim: implement Part.

    whitequark committed Dec 15, 2018
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    20a04bc View commit details
Showing with 23 additions and 13 deletions.
  1. +2 −2 doc/COMPAT_SUMMARY.md
  2. +5 −5 examples/{clkdiv.py → ctr.py}
  3. +4 −4 examples/{ctrl.py → ctr_ce.py}
  4. +5 −1 nmigen/back/pysim.py
  5. +1 −1 nmigen/hdl/ast.py
  6. +6 −0 nmigen/test/test_sim.py
4 changes: 2 additions & 2 deletions doc/COMPAT_SUMMARY.md
Original file line number Diff line number Diff line change
@@ -37,8 +37,8 @@ Compatibility summary
<br>Note: `transform_*` methods not considered part of public API.
- (⊙) `ModuleTransformer` **brk**
- (⊙) `ControlInserter` **brk**
- (+) `CEInserter` id, `clock_domains=``controls=`
- (+) `ResetInserter` id, `clock_domains=``controls=`
- (-) `CEInserter` **obs**
- (-) `ResetInserter` **obs**
- (+) `ClockDomainsRenamer``DomainRenamer`, `cd_remapping=``domain_map=`
- (⊙) `edif` **brk**
- (+) `module` **obs**`.hdl.dsl`
10 changes: 5 additions & 5 deletions examples/clkdiv.py → examples/ctr.py
Original file line number Diff line number Diff line change
@@ -2,9 +2,9 @@
from nmigen.back import rtlil, verilog, pysim


class ClockDivisor:
def __init__(self, factor):
self.v = Signal(factor, reset=2**factor-1)
class Counter:
def __init__(self, width):
self.v = Signal(width, reset=2**width-1)
self.o = Signal()

def get_fragment(self, platform):
@@ -14,13 +14,13 @@ def get_fragment(self, platform):
return m.lower(platform)


ctr = ClockDivisor(factor=16)
ctr = Counter(width=16)
frag = ctr.get_fragment(platform=None)

# print(rtlil.convert(frag, ports=[ctr.o]))
print(verilog.convert(frag, ports=[ctr.o]))

with pysim.Simulator(frag,
vcd_file=open("clkdiv.vcd", "w")) as sim:
vcd_file=open("ctr.vcd", "w")) as sim:
sim.add_clock(1e-6)
sim.run_until(100e-6, run_passive=True)
8 changes: 4 additions & 4 deletions examples/ctrl.py → examples/ctr_ce.py
Original file line number Diff line number Diff line change
@@ -2,9 +2,9 @@
from nmigen.back import rtlil, verilog, pysim


class ClockDivisor:
def __init__(self, factor):
self.v = Signal(factor, reset=2**factor-1)
class Counter:
def __init__(self, width):
self.v = Signal(width, reset=2**width-1)
self.o = Signal()
self.ce = Signal()

@@ -15,7 +15,7 @@ def get_fragment(self, platform):
return CEInserter(self.ce)(m.lower(platform))


ctr = ClockDivisor(factor=16)
ctr = Counter(width=16)
frag = ctr.get_fragment(platform=None)

# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
6 changes: 5 additions & 1 deletion nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -118,7 +118,11 @@ def on_Slice(self, value):
return lambda state: normalize((arg(state) >> shift) & mask, shape)

def on_Part(self, value):
raise NotImplementedError
shape = value.shape()
arg = self(value.value)
shift = self(value.offset)
mask = (1 << value.width) - 1
return lambda state: normalize((arg(state) >> shift(state)) & mask, shape)

def on_Cat(self, value):
shape = value.shape()
2 changes: 1 addition & 1 deletion nmigen/hdl/ast.py
Original file line number Diff line number Diff line change
@@ -405,7 +405,7 @@ def _lhs_signals(self):
return self.value._lhs_signals()

def _rhs_signals(self):
return self.value._rhs_signals()
return self.value._rhs_signals() | self.offset._rhs_signals()

def __repr__(self):
return "(part {} {} {})".format(repr(self.value), repr(self.offset), self.width)
6 changes: 6 additions & 0 deletions nmigen/test/test_sim.py
Original file line number Diff line number Diff line change
@@ -130,6 +130,12 @@ def test_slice(self):
stmt2 = lambda a: a[2:4]
self.assertOperator(stmt2, [C(0b10110100, 8)], C(0b01, 2))

def test_part(self):
stmt = lambda a, b: a.part(b, 3)
self.assertOperator(stmt, [C(0b10110100, 8), C(0)], C(0b100, 3))
self.assertOperator(stmt, [C(0b10110100, 8), C(2)], C(0b101, 3))
self.assertOperator(stmt, [C(0b10110100, 8), C(3)], C(0b110, 3))

def test_cat(self):
self.assertOperator(Cat, [C(0b10, 2), C(0b01, 2)], C(0b0110, 4))