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The statement m.comb += ResetSignal().eq(0) can be used in principle to tie the reset signal of a clock domain low (and remove the rst signal from the top-level port list). However, as-is a backtrace similar to the following results:
William@William-THINK MINGW64 ~/src/migen_mercury/baseboard
$ python3 baseboard.py
Traceback (most recent call last):
File "baseboard.py", line 373, in <module>
m.comb += ResetSignal().eq(0)
File "C:/msys64/home/william/src/nmigen\nmigen\tools.py", line 52, in wrapper
return f(*args, **kwargs)
File "C:/msys64/home/william/src/nmigen\nmigen\compat\fhdl\module.py", line 32, in __iadd__
self._cm._module._add_statement(assigns, domain=None, depth=0, compat_mode=True)
File "C:/msys64/home/william/src/nmigen\nmigen\hdl\dsl.py", line 248, in _add_statement
for signal in assign._lhs_signals():
File "C:/msys64/home/william/src/nmigen\nmigen\hdl\ast.py", line 813, in _lhs_signals
return self.lhs._lhs_signals()
File "C:/msys64/home/william/src/nmigen\nmigen\hdl\ast.py", line 194, in _lhs_signals
raise TypeError("Value {!r} cannot be used in assignments".format(self))
TypeError: Value (rst sync) cannot be used in assignments
Workaround for the time being is to manually declare the clock domain with reset_less=True.
The text was updated successfully, but these errors were encountered:
whitequark
changed the title
Tying ResetSignal to Constant Value results in backtrace.
Tying ResetSignal to Constant Value results in exception
Dec 18, 2018
whitequark
changed the title
Tying ResetSignal to Constant Value results in exception
ClockSignal/ResetSignal cannot be used on LHS
Jan 8, 2019
The statement
m.comb += ResetSignal().eq(0)
can be used in principle to tie the reset signal of a clock domain low (and remove therst
signal from the top-level port list). However, as-is a backtrace similar to the following results:Workaround for the time being is to manually declare the clock domain with
reset_less=True
.The text was updated successfully, but these errors were encountered: