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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 9bce35098f65
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  • 3 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 16, 2018

  1. back.rtlil: don't emit a slice if all bits are used.

    whitequark committed Dec 16, 2018
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    2833b36 View commit details
  2. Copy the full SHA
    e86104d View commit details
  3. back.rtlil: avoid illegal slices.

    Not sure what to do with {} [] on LHS yet--fix Yosys?
    whitequark committed Dec 16, 2018
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    9bce350 View commit details
Showing with 42 additions and 19 deletions.
  1. +42 −19 nmigen/back/rtlil.py
61 changes: 42 additions & 19 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -272,12 +272,6 @@ def on_ClockSignal(self, value):
def on_ResetSignal(self, value):
raise NotImplementedError # :nocov:

def on_Slice(self, value):
if value.end == value.start + 1:
return "{} [{}]".format(self(value.value), value.start)
else:
return "{} [{}:{}]".format(self(value.value), value.end - 1, value.start)

def on_Cat(self, value):
return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands])))

@@ -337,19 +331,19 @@ def match_shape(self, value, new_bits, new_sign):
return self(ast.Const(value.value, (new_bits, new_sign)))

value_bits, value_sign = value.shape()
if new_bits > value_bits:
res = self.s.rtlil.wire(width=new_bits)
self.s.rtlil.cell("$pos", ports={
"\\A": self(value),
"\\Y": res,
}, params={
"A_SIGNED": value_sign,
"A_WIDTH": value_bits,
"Y_WIDTH": new_bits,
}, src=src(value.src_loc))
return res
else:
return "{} [{}:0]".format(self(value), new_bits - 1)
if new_bits <= value_bits:
return self(ast.Slice(value, 0, new_bits))

res = self.s.rtlil.wire(width=new_bits)
self.s.rtlil.cell("$pos", ports={
"\\A": self(value),
"\\Y": res,
}, params={
"A_SIGNED": value_sign,
"A_WIDTH": value_bits,
"Y_WIDTH": new_bits,
}, src=src(value.src_loc))
return res

def on_Operator_binary(self, value):
lhs, rhs = value.operands
@@ -408,6 +402,21 @@ def on_Operator(self, value):
else:
raise TypeError # :nocov:

def on_Slice(self, value):
if value.start == 0 and value.end == len(value.value):
return self(value.value)

if isinstance(value.value, ast.Signal):
sigspec = self(value.value)
else:
sigspec = self.s.rtlil.wire(len(value.value))
self.s.rtlil.connect(sigspec, self(value.value))

if value.start + 1 == value.end:
return "{} [{}]".format(sigspec, value.start)
else:
return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)

def on_Part(self, value):
raise NotImplementedError

@@ -431,6 +440,20 @@ def on_Signal(self, value):
raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(value)))
return wire_next

def on_Slice(self, value):
if value.start == 0 and value.end == len(value.value):
return self(value.value)

if isinstance(value.value, ast.Signal):
sigspec = self(value.value)
else:
raise NotImplementedError

if value.start + 1 == value.end:
return "{} [{}]".format(sigspec, value.start)
else:
return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)

def on_Part(self, value):
raise NotImplementedError