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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 16, 2018

  1. README: mention Yosys requirement.

    whitequark committed Dec 16, 2018
    Copy the full SHA
    41d69c3 View commit details
  2. back.rtlil: properly escape strings in attributes.

    whitequark committed Dec 16, 2018
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    6350943 View commit details
Showing with 24 additions and 12 deletions.
  1. +5 −2 README.md
  2. +19 −10 nmigen/back/rtlil.py
7 changes: 5 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
@@ -12,9 +12,12 @@ Other nMigen libraries are built on FHDL and provide various tools such as a sys

See the [doc/](doc/) folder for more technical information.

nMigen is a direct descendant of [Migen](https://m-labs.hk/migen) rewritten from scratch to address many issues that became clear in the many years Migen has been used in production. nMigen provides an extensive compatibility layer that makes it possible to build and simulate most Migen designs unmodified, as well as integrate modules written for Migen and nMigen.
nMigen is a direct descendant of [Migen][] rewritten from scratch to address many issues that became clear in the many years Migen has been used in production. nMigen provides an extensive compatibility layer that makes it possible to build and simulate most Migen designs unmodified, as well as integrate modules written for Migen and nMigen.

nMigen is designed for Python 3.6 and newer. Note that nMigen is **not** spelled nMiGen.
nMigen is designed for Python 3.6 and newer. nMigen's Verilog backend depends on [Yosys][]; currently, the `master` branch of Yosys is required.

[migen]: https://m-labs.hk/migen
[yosys]: http://www.clifford.at/yosys/

### Introduction

29 changes: 19 additions & 10 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -26,6 +26,13 @@ def _make_name(self, name, local):


class _Bufferer:
_escape_map = str.maketrans({
"\"": "\\\"",
"\\": "\\\\",
"\t": "\\t",
"\r": "\\r",
"\n": "\\n",
})
def __init__(self):
super().__init__()
self._buffer = io.StringIO()
@@ -36,9 +43,17 @@ def __str__(self):
def _append(self, fmt, *args, **kwargs):
self._buffer.write(fmt.format(*args, **kwargs))

def attribute(self, name, value, indent=0):
if isinstance(value, str):
self._append("{}attribute \\{} \"{}\"\n",
" " * indent, name, value.translate(self._escape_map))
else:
self._append("{}attribute \\{} {}\n",
" " * indent, name, int(value))

def _src(self, src):
if src:
self._append(" attribute \\src \"{}\"\n", src.replace("\"", "\\\""))
self.attribute("src", src)


class _Builder(_Namer, _Bufferer):
@@ -57,22 +72,16 @@ def __init__(self, rtlil, name, attrs):

def __enter__(self):
for name, value in self.attrs.items():
if isinstance(value, str):
self._append("attribute \\{} \"{}\"\n", name, value.replace("\"", "\\\""))
else:
self._append("attribute \\{} {}\n", name, int(value))
self.attribute(name, value, indent=0)
self._append("module {}\n", self.name)
return self

def __exit__(self, *args):
self._append("end\n")
self.rtlil._buffer.write(str(self))

def attribute(self, name, value):
if isinstance(value, str):
self._append(" attribute \\{} \"{}\"\n", name, value.replace("\"", "\\\""))
else:
self._append(" attribute \\{} {}\n", name, int(value))
def attribute(self, name, value, indent=1):
super().attribute(name, value, indent)

def wire(self, width, port_id=None, port_kind=None, name=None, src=""):
self._src(src)