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base repository: timvideos/HDMI2USB-litex-firmware
base: a33050bfddce
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head repository: timvideos/HDMI2USB-litex-firmware
compare: 4383c27278e0
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  • 18 commits
  • 14 files changed
  • 2 contributors

Commits on Nov 8, 2018

  1. Updating submodules.

     * litedram changed from f36bcff to 69ea866
        *   69ea866 - Merge pull request #62 from daveshah1/AS4C32M16 <enjoy-digital>
        |\
        | * 3a5d45b - modules: Add AS4C32M16 32Mx16 SDRAM <David Shah>
        * | b41fe61 - phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering <Florent Kermarrec>
        * | 2e19787 - phy/kusddrphy: add dfi mux on address/control signals <Florent Kermarrec>
        * | a8c3d39 - sdram_init: fix compilation <Florent Kermarrec>
        * | af34489 - common: add DDR4 burst_length <Florent Kermarrec>
        * | 2a9fb11 - phy/kusddrphy: more genericity, initial DDR4 support <Florent Kermarrec>
        * | ae5dc9f - sdram_init: add initial DDR4 initialization <Florent Kermarrec>
        * | 8181fea - modules: add EDY4016A DDR4 <Florent Kermarrec>
        * | 346e64c - frontend/ecc: fix typo <Florent Kermarrec>
        |/
        * 82c08c7 - phy/gensdrphy: use tristate input <Florent Kermarrec>
        * 9ce84d9 - modules: add MT48LC16M16 (ulx3s) <Florent Kermarrec>
    
     * liteeth changed from 40b99ec to 52c2301
        * 52c2301 - frontend/etherbone: reduce default buffer_depth to 4 <Florent Kermarrec>
        * 602ddec - common: use reverse_bytes from litex.gen <Florent Kermarrec>
    
     * litepcie changed from a8b8048 to 80f28b1
        * 80f28b1 - common: use reverse_bits/reverse_bytes from litex.gen <Florent Kermarrec>
    
     * litex changed from 98159209 to fc0d5c39
        * fc0d5c39 - bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients <Florent Kermarrec>
        * 09f962fd - target/kcu105: add reset button <Florent Kermarrec>
        * 169f8d8c - boards/platforms/kcu105: fix sdram/dq pin swap <Florent Kermarrec>
        * 2624ba48 - bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 <Florent Kermarrec>
        * 6be74aa1 - boards/targets: add kcu105 <Florent Kermarrec>
        *   93c62325 - Merge pull request #122 from daveshah1/trellis_ulx3s <enjoy-digital>
        |\
        | * 0729b3a0 - ulx3s: Connect SDRAM clock <David Shah>
        | * 84044349 - Fix Trellis build; ULX3S demo boots to BIOS <David Shah>
        | * 0c1d8d59 - trellis: Switch to using LPF for constraints <David Shah>
        * |   00ef8240 - Merge pull request #124 from jfng/master <enjoy-digital>
        |\ \
        | * | dcbe759b - build/sim/verilator: don't use --threads when $(THREADS) is unset <Jean-François Nguyen>
        |/ /
        * | 6f38213a - boards/platforms/kc705: add user_sma_mgt_refclk <Florent Kermarrec>
        * |   4cdd6799 - Merge pull request #123 from cr1901/prv32-min <enjoy-digital>
        |\ \
        | * | e56f7182 - libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). <William D. Jones>
        | * | f32121e0 - cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. <William D. Jones>
        | * | 77389d27 - libbase/crt0-picorv32: Ensure BSS is cleared on boot. <William D. Jones>
        | * | f69bd877 - cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). <William D. Jones>
        | * | d05fe673 - cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. <William D. Jones>
        * | | f7969b66 - cores/clock: add with_reset parameter (default to True) <Florent Kermarrec>
        | |/
        |/|
        * | 445c4940 - boards/platforms/kcu105: add sfp_tx/rx definition <Florent Kermarrec>
        |/
        * e9d4c882 - build/lattice/prjtrellis: fix default toolchain_path <Florent Kermarrec>
        * 468780c0 - soc/cores/spi_flash: add endianness parameter <Florent Kermarrec>
        * 6f3131e2 - soc/interconnect/stream_packet: use reverse_bytes from litex.gen <Florent Kermarrec>
        * b7968538 - gen: add common with reverse_bits/reverse_bytes functions <Florent Kermarrec>
        * 71fc34d7 - boards/targets/ulx3s: reduce l2_size <Florent Kermarrec>
        * 75d073f3 - build/lattice/prjtrellis: fix typo <Florent Kermarrec>
        * 6048a529 - build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts. <Florent Kermarrec>
        * 2243f628 - build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl <Florent Kermarrec>
        *   3a8bb94a - Merge pull request #121 from cr1901/patch-3 <Tim Ansell>
        |\
        | * f3111e11 - Update vivado.py <William D. Jones>
        |/
        * 98fa8996 - boards/targets: add ulx3s <Florent Kermarrec>
        * 7d779473 - boards/platforms: add ulx3s <Florent Kermarrec>
        * d9dcad33 - build/lattice/prjtrellis: add inout support <Florent Kermarrec>
        * 091ad799 - build/lattice/common: add tristate support <Florent Kermarrec>
        * 23acefb1 - boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed <Florent Kermarrec>
        * 1097f822 - build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis" <Florent Kermarrec>
        * 52917a71 - boards/targets/simple: add gateware-toolchain parameter <Florent Kermarrec>
        * d84083f6 - boards/platforms/versaecp55g: use ftdi serial pins <Florent Kermarrec>
        * c05b9ef2 - build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support <Florent Kermarrec>
        * a8f819fe - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
        * 4eb314a2 - boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :) <Florent Kermarrec>
        * 27ec2a59 - build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO <Florent Kermarrec>
        * c506c975 - gen/fhdl/verilog: set direction to io signals <Florent Kermarrec>
    
     * migen changed from 0.6.dev-179-g657c0c7 to 0.6.dev-187-gc79d988
        * c79d988 - build/platforms/versaecp55g: add X3 external connector. <whitequark>
        * d60cea0 - build/platforms/versaecp55g: add external clock input. <whitequark>
        * c51a064 - build/platforms/versaecp55g: allow programming without ispCLOCK in chain. <whitequark>
        * 34eeb3b - build/platforms/versaecp55g: import from litex. <whitequark>
        * 7bdc4ed - build/lattice/diamond: add Linux support. <whitequark>
        * 3a84a8b - build/lattice/diamond: only run Jedecgen for MachXO. <whitequark>
        * 966781b - class Tristate: add support for target parameter with oe, o and i subsignals. (#148) <Staf Verhaegen>
        * 907afd5 - platforms/icebreaker: Rename I/O w/ @esden's feedback. <William D. Jones>
    
    Full submodule status
    --
     5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
     69ea8668d06f3973e2342a1f8bc3ace2ca37f808 litedram (remotes/origin/HEAD)
     52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
     80f28b1dd4d67c37a3829fbeef725a3ca8efad79 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
     13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
     fc0d5c3963146f67ad03ba0c6bdf06a6b4a0cde6 litex (heads/master)
     c79d98882088ceb23b9095002d08ad93a81d0021 migen (0.6.dev-187-gc79d988)
    cr1901 committed Nov 8, 2018
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Commits on Nov 20, 2018

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  7. Revert "scripts/build-micropython.sh: Fix detection of RISCV compilers."

    riscv32-elf-gcc is provided after all.
    
    This reverts commit afd259a.
    cr1901 committed Nov 20, 2018
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  9. travis.yml: Fix formatting.

    cr1901 committed Nov 20, 2018
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  10. Merge pull request #105 from cr1901/riscv32

    Riscv32 Support
    mithro committed Nov 20, 2018
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Commits on Nov 21, 2018

  1. Updating submodules.

     * litedram changed from 30d9a3e to bc6a3f2
        * bc6a3f2 - examples/sim/sim/py: remove apb interface <Florent Kermarrec>
        * e7e4bc5 - examples/sim: add ddr3 micron model <Florent Kermarrec>
        * f219693 - examples: add simulation <Florent Kermarrec>
    
     * litepcie changed from 48f662e to dddd3b1
        * dddd3b1 - phy/s7pciephy: fix soft reset by reseting pcie on cd reset <Florent Kermarrec>
    
     * litevideo changed from 13d85a1 to 0993a4e
        * 0993a4e - Merge pull request #21 from felixheld/licensefix <Tim Ansell>
        * d8287db - LICENSE: use right project name <Felix Held>
    
     * litex changed from bc173380 to ab799f7b
        *   ab799f7b - Merge pull request #127 from cr1901/picorv32-data <Tim Ansell>
        |\
        | * 89c70218 - libbase/crt0-picorv32: Add support for .data sections. <William D. Jones>
        |/
        * 80bdae0e - build/sim/verilator: add trace parameter to enable tracer <Florent Kermarrec>
        * 7359a99b - soc_core: convert cpu_type="None" string to None <Florent Kermarrec>
        * 5805d630 - build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route <Florent Kermarrec>
        * 85f76662 - build/microsemi/common: add async reset synchronizer (using DFN1P0) <Florent Kermarrec>
        * e3c6bd58 - build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools <Florent Kermarrec>
        * 4c966114 - build/microsemi/libero_soc: add timing constraints support <Florent Kermarrec>
        * 60faae49 - boards/platforms/avalanche: fix swapped serial pins <Florent Kermarrec>
        * 52396add - boards/platforms/avalanche: rename rst to rst_n (active low reset) <Florent Kermarrec>
        * 8e07e1a0 - build/microsemi/libero_soc: associate .pdc to place and route tool. <Florent Kermarrec>
        * 5137c2bf - test/test_targets: update <Florent Kermarrec>
        * a5ed42ec - soc/interconnect/stream: add Gearbox <Florent Kermarrec>
        * 11d536dc - test: remove test_bitslip (integrated in migen) <Florent Kermarrec>
        * a25645af - utils: add litex_read_verilog utility <Florent Kermarrec>
        * a538d362 - create utils directory and move the litex utils to it <Florent Kermarrec>
        * 45ec78e9 - build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board. <Florent Kermarrec>
        * 4cb6583b - build: add microsemi template for polarfire fpgas support <Florent Kermarrec>
    
     * migen changed from 0.6.dev-209-gc285c12 to 0.6.dev-211-g022721a
        * 022721a - lattice/diamond: Support sourcing by default. <William D. Jones>
        * 17e6d34 - fix yosys commands for build_names other than 'top' <Erin Moon>
    
    Full submodule status
    --
     5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
     bc6a3f220a16fbc1208cc23ab5cf072d2b81f62e litedram (remotes/origin/HEAD)
     52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
     dddd3b16edfc9b345526f4106954b2c6b6f00933 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (remotes/origin/HEAD)
     ab799f7bd7e0ad2063747dc6636de61225e648c4 litex (remotes/origin/HEAD)
     022721a81d274a08ccb1b1f7919d4940cce99a73 migen (0.6.dev-211-g022721a)
    cr1901 committed Nov 21, 2018
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  2. Merge pull request #106 from cr1901/picorv32-data

    Updating submodules.
    mithro committed Nov 21, 2018
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Commits on Dec 9, 2018

  1. Fix script line in README

    Fixes #107.
    mithro committed Dec 9, 2018
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