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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 9307a316781d
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 14, 2018

  1. back.pysim: better naming. NFC.

    whitequark committed Dec 14, 2018
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    e3f32a1 View commit details
  2. back.pysim: Simulator({gtkw_signals→traces}=).

    whitequark committed Dec 14, 2018
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    9307a31 View commit details
Showing with 10 additions and 11 deletions.
  1. +1 −1 examples/ctrl.py
  2. +8 −9 nmigen/back/pysim.py
  3. +1 −1 nmigen/test/test_sim.py
2 changes: 1 addition & 1 deletion examples/ctrl.py
Original file line number Diff line number Diff line change
@@ -24,7 +24,7 @@ def get_fragment(self, platform):
with pysim.Simulator(frag,
vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"),
gtkw_signals=[ctr.ce, ctr.v, ctr.o]) as sim:
traces=[ctr.ce, ctr.v, ctr.o]) as sim:
sim.add_clock(1e-6)
def ce_proc():
yield; yield; yield
17 changes: 8 additions & 9 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -191,7 +191,7 @@ def run(state):


class Simulator:
def __init__(self, fragment, vcd_file=None, gtkw_file=None, gtkw_signals=()):
def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._fragment = fragment

self._domains = {} # str/domain -> ClockDomain
@@ -221,9 +221,8 @@ def __init__(self, fragment, vcd_file=None, gtkw_file=None, gtkw_signals=()):
self._vcd_writer = None
self._vcd_signals = ValueDict() # signal -> set(vcd_signal)
self._vcd_names = ValueDict() # signal -> str/name

self._gtkw_file = gtkw_file
self._gtkw_signals = gtkw_signals
self._traces = traces

def _check_process(self, process):
if inspect.isgeneratorfunction(process):
@@ -279,14 +278,14 @@ def __enter__(self):
self._domain_triggers[cd.rst] = domain
self._domain_signals[domain] = ValueSet()

fragment_names = {}
def add_fragment(fragment, hierarchy=("top",)):
fragment_names[fragment] = hierarchy
hierarchy = {}
def add_fragment(fragment, scope=("top",)):
hierarchy[fragment] = scope
for subfragment, name in fragment.subfragments:
add_fragment(subfragment, (*hierarchy, name))
add_fragment(subfragment, (*scope, name))
add_fragment(root_fragment)

for fragment, fragment_name in fragment_names.items():
for fragment, fragment_name in hierarchy.items():
for signal in fragment.iter_signals():
self._signals.add(signal)

@@ -578,7 +577,7 @@ def add_trace(signal, **kwargs):
add_trace(cd.rst)
add_trace(cd.clk)

for signal in self._gtkw_signals:
for signal in self._traces:
add_trace(signal)

if self._vcd_file:
2 changes: 1 addition & 1 deletion nmigen/test/test_sim.py
Original file line number Diff line number Diff line change
@@ -19,7 +19,7 @@ def assertOperator(self, stmt, inputs, output):
with Simulator(frag,
vcd_file =open("test.vcd", "w"),
gtkw_file=open("test.gtkw", "w"),
gtkw_signals=[*isigs, osig]) as sim:
traces=[*isigs, osig]) as sim:
def process():
for isig, input in zip(isigs, inputs):
yield isig.eq(input)