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base repository: m-labs/nmigen
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base: a10791e160bb
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head repository: m-labs/nmigen
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compare: 6aefd0c04c92
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 14, 2018

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    6aefd0c View commit details
Showing with 15 additions and 1 deletion.
  1. +15 −1 nmigen/back/pysim.py
16 changes: 15 additions & 1 deletion nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -7,7 +7,11 @@
from ..fhdl.xfrm import ValueTransformer, StatementTransformer


__all__ = ["Simulator", "Delay", "Passive"]
__all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]


class DeadlineError(Exception):
pass


class _State:
@@ -426,9 +430,19 @@ def _run_process(self, proc):
.format(stmt, proc))

def step(self, run_passive=False):
deadline = None
if self._wait_deadline:
# We might run some delta cycles, and we have simulator processes waiting on
# a deadline. Take care to not exceed the closest deadline.
deadline = min(self._wait_deadline.values())

# Are there any delta cycles we should run?
while self._state.curr_dirty:
self._timestamp += self._epsilon
if deadline is not None and self._timestamp >= deadline:
# Oops, we blew the deadline. We *could* run the processes now, but this is
# virtually certainly a logic loop and a design bug, so bail out instead.d
raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")

domains = set()
self._update_dirty_signals()