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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 625c55a3b899
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 14, 2018

  1. back.pysim: add gtkw traces even more robustly.

    whitequark committed Dec 14, 2018
    Copy the full SHA
    654722c View commit details
  2. back.pysim: throw exceptions back at processes.

    whitequark committed Dec 14, 2018
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    625c55a View commit details
Showing with 14 additions and 8 deletions.
  1. +14 −8 nmigen/back/pysim.py
22 changes: 14 additions & 8 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -489,6 +489,9 @@ def _run_process(self, process):
self._processes.remove(process)
self._passive.discard(process)

except Exception as e:
process.throw(e)

def step(self, run_passive=False):
deadline = None
if self._wait_deadline:
@@ -556,16 +559,19 @@ def __exit__(self, *args):
gtkw_save.treeopen("top")
gtkw_save.zoom_markers(math.log(self._epsilon / self._fastest_clock) - 14)

for domain, cd in self._domains.items():
with gtkw_save.group("d.{}".format(domain)):
if cd.rst is not None:
gtkw_save.trace(self._vcd_names[cd.rst])
gtkw_save.trace(self._vcd_names[cd.clk])

for signal in self._gtkw_signals:
def add_trace(signal, **kwargs):
if signal in self._vcd_names:
if len(signal) > 1:
suffix = "[{}:0]".format(len(signal) - 1)
else:
suffix = ""
gtkw_save.trace(self._vcd_names[signal] + suffix)
gtkw_save.trace(self._vcd_names[signal] + suffix, **kwargs)

for domain, cd in self._domains.items():
with gtkw_save.group("d.{}".format(domain)):
if cd.rst is not None:
add_trace(cd.rst)
add_trace(cd.clk)

for signal in self._gtkw_signals:
add_trace(signal)