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base repository: m-labs/nmigen
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base: b58715c5dc25
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head repository: m-labs/nmigen
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compare: b34c1a9ad083
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Dec 14, 2018

  1. Copy the full SHA
    b34c1a9 View commit details
Showing with 8 additions and 2 deletions.
  1. +6 −1 nmigen/back/pysim.py
  2. +2 −1 nmigen/fhdl/ir.py
7 changes: 6 additions & 1 deletion nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -326,8 +326,13 @@ def __enter__(self):
self._sync_signals.update(signals)
self._domain_signals[domain].update(signals)

statements = []
for signal in fragment.iter_comb():
statements.append(signal.eq(signal.reset))
statements += fragment.statements

compiler = _StatementCompiler()
funclet = compiler(fragment.statements)
funclet = compiler(statements)
for signal in compiler.sensitivity:
self._add_funclet(signal, funclet)
for domain, cd in fragment.domains.items():
3 changes: 2 additions & 1 deletion nmigen/fhdl/ir.py
Original file line number Diff line number Diff line change
@@ -39,7 +39,8 @@ def iter_drivers(self):
yield domain, signal

def iter_comb(self):
yield from self.drivers[None]
if None in self.drivers:
yield from self.drivers[None]

def iter_sync(self):
for domain, signals in self.drivers.items():