Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 6aefd0c04c92
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: b58715c5dc25
Choose a head ref
  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 14, 2018

  1. back.pysim: fix completely broken codegen for Switch.

    whitequark committed Dec 14, 2018
    Copy the full SHA
    bb843cb View commit details
  2. Copy the full SHA
    b58715c View commit details
Showing with 29 additions and 12 deletions.
  1. +19 −6 nmigen/back/pysim.py
  2. +3 −4 nmigen/compat/genlib/fsm.py
  3. +7 −2 nmigen/fhdl/ast.py
25 changes: 19 additions & 6 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -169,14 +169,15 @@ def on_Switch(self, stmt):
mask = "1" * len(value)
mask = int(mask, 2)
value = int(value, 2)
cases.append((lambda test: test & mask == value,
self.on_statements(stmts)))
def make_test(mask, value):
return lambda test: test & mask == value
cases.append((make_test(mask, value), self.on_statements(stmts)))
def run(state):
test_value = test(state)
for check, body in cases:
if check(test_value):
body(state)
return
return
return run

def on_statements(self, stmts):
@@ -294,6 +295,14 @@ def __enter__(self):
self._vcd_signals[signal] = set()
name = self._signal_name_in_fragment(fragment, signal)
suffix = None
if signal.decoder:
var_type = "string"
var_size = 1
var_init = signal.decoder(signal.reset).replace(" ", "_")
else:
var_type = "wire"
var_size = signal.nbits
var_init = signal.reset
while True:
try:
if suffix is None:
@@ -302,7 +311,7 @@ def __enter__(self):
name_suffix = "{}${}".format(name, suffix)
self._vcd_signals[signal].add(self._vcd_writer.register_var(
scope=".".join(self._fragments[fragment]), name=name_suffix,
var_type="wire", size=signal.nbits, init=signal.reset))
var_type=var_type, size=var_size, init=var_init))
if signal not in self._vcd_names:
self._vcd_names[signal] = \
".".join(self._fragments[fragment] + (name_suffix,))
@@ -355,10 +364,14 @@ def _commit_signal(self, signal, domains):
if (old, new) == (0, 1) and signal in self._domain_triggers:
domains.add(self._domain_triggers[signal])

if self._vcd_writer:
if self._vcd_writer and old != new:
# Finally, dump the new value to the VCD file.
for vcd_signal in self._vcd_signals[signal]:
self._vcd_writer.change(vcd_signal, self._timestamp / self._epsilon, new)
if signal.decoder:
var_value = signal.decoder(new).replace(" ", "_")
else:
var_value = new
self._vcd_writer.change(vcd_signal, self._timestamp / self._epsilon, var_value)

def _commit_comb_signals(self, domains):
"""Perform the comb part of IR processes (aka RTLIL always)."""
7 changes: 3 additions & 4 deletions nmigen/compat/genlib/fsm.py
Original file line number Diff line number Diff line change
@@ -156,10 +156,9 @@ def do_finalize(self):
self.encoding = dict((s, n) for n, s in enumerate(self.actions.keys()))
self.decoding = {n: s for s, n in self.encoding.items()}

self.state = Signal(max=nstates, reset=self.encoding[self.reset_state])
self.state._enumeration = self.decoding
self.next_state = Signal(max=nstates)
self.next_state._enumeration = {n: "{}:{}".format(n, s) for n, s in self.decoding.items()}
decoder = lambda n: "{}/{}".format(self.decoding[n], n)
self.state = Signal(max=nstates, reset=self.encoding[self.reset_state], decoder=decoder)
self.next_state = Signal.like(self.state)

for state, signal in self.before_leaving_signals.items():
encoded = self.encoding[state]
9 changes: 7 additions & 2 deletions nmigen/fhdl/ast.py
Original file line number Diff line number Diff line change
@@ -512,6 +512,9 @@ class Signal(Value, DUID):
defaults to 0) and ``max`` (exclusive, defaults to 2).
attrs : dict
Dictionary of synthesis attributes.
decoder : function
A function converting integer signal values to human-readable strings (e.g. FSM state
names).
Attributes
----------
@@ -524,7 +527,7 @@ class Signal(Value, DUID):
"""

def __init__(self, shape=None, name=None, reset=0, reset_less=False, min=None, max=None,
attrs=None, src_loc_at=0):
attrs=None, decoder=None, src_loc_at=0):
super().__init__(src_loc_at=src_loc_at)

if name is None:
@@ -560,6 +563,7 @@ def __init__(self, shape=None, name=None, reset=0, reset_less=False, min=None, m
self.reset_less = bool(reset_less)

self.attrs = OrderedDict(() if attrs is None else attrs)
self.decoder = decoder

@classmethod
def like(cls, other, src_loc_at=0, **kwargs):
@@ -573,7 +577,8 @@ def like(cls, other, src_loc_at=0, **kwargs):
kw = dict(shape=cls.wrap(other).shape(),
name=tracer.get_var_name(depth=2 + src_loc_at))
if isinstance(other, cls):
kw.update(reset=other.reset, reset_less=other.reset_less, attrs=other.attrs)
kw.update(reset=other.reset, reset_less=other.reset_less,
attrs=other.attrs, decoder=other.decoder)
kw.update(kwargs)
return cls(**kw, src_loc_at=1 + src_loc_at)