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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: f96867893703
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 16, 2018

  1. back.rtlil: handle reset_less domains.

    whitequark committed Dec 16, 2018
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    f968678 View commit details
Showing with 2 additions and 1 deletion.
  1. +2 −1 nmigen/back/rtlil.py
3 changes: 2 additions & 1 deletion nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -515,7 +515,8 @@ def convert_fragment(builder, fragment, name, top):
for domain, _ in fragment.iter_sync():
cd = fragment.domains[domain]
compiler_state.resolve_curr(cd.clk)
compiler_state.resolve_curr(cd.rst)
if cd.rst is not None:
compiler_state.resolve_curr(cd.rst)

# Transform all subfragments to their respective cells. Transforming signals connected
# to their ports into wires eagerly makes sure they get sensible (prefixed with submodule