Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: whitequark/glasgow
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 911d659c4a3b
Choose a base ref
...
head repository: whitequark/glasgow
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 2e9675c191b6
Choose a head ref
  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 3, 2018

  1. gateware.boneless: implement MOVH, MOVL and MOVA.

    @whitequark
    whitequark committed Dec 3, 2018
    Copy the full SHA
    2861922 View commit details

  2. gateware.boneless: implement ADDI.

    @whitequark
    whitequark committed Dec 3, 2018
    Copy the full SHA
    2e9675c View commit details
Showing with 79 additions and 16 deletions.
  1. +1 −1 software/glasgow/arch/boneless/instr.py
  2. +2 −2 software/glasgow/arch/boneless/opcode.py
  3. +76 −13 software/glasgow/gateware/boneless.py
2 changes: 1 addition & 1 deletion software/glasgow/arch/boneless/instr.py
View file
Original file line number Diff line number Diff line change
@@ -121,7 +121,7 @@ def MOVI(rd, imm16):
return MOVL(rd, imm16)
else:
return MOVH(rd, (imm16 >> 8) + ((imm16 >> 7) & 1)) + \
I_FORMAT(OPCODE_ADDI, rd, imm16 & 0xff, u=True)
[I_FORMAT(OPCODE_ADDI, rd, imm16 & 0xff, u=True)]


def L(label): return label
4 changes: 2 additions & 2 deletions software/glasgow/arch/boneless/opcode.py
View file
Original file line number Diff line number Diff line change
@@ -30,10 +30,10 @@
OPCODE_MOVL = 0b01_000
OPCODE_MOVH = 0b01_001
OPCODE_MOVA = 0b01_010
OPCODE_JAL = 0b01_011
OPCODE_ADDI = 0b01_011
OPCODE_LDI = 0b01_100
OPCODE_STI = 0b01_101
OPCODE_ADDI = 0b01_110
OPCODE_JAL = 0b01_110
OPCODE_JR = 0b01_111

OPCODE_F_0 = 0b1_000
89 changes: 76 additions & 13 deletions software/glasgow/gateware/boneless.py
View file
Original file line number Diff line number Diff line change
@@ -17,12 +17,19 @@ def AddSignedImm(v, i):
return v + Cat(i, Replicate(i[i_nbits - 1], v.nbits - i_nbits))


class DummyExtPort(Module):
def __init__(self):
self.adr = Signal(16)
self.dat_r = Signal(16)
self.re = Signal()
self.dat_w = Signal(16)
self.we = Signal()


class BonelessCore(Module):
def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
if ext_port is None:
ext_port = _MemoryPort(adr=Signal(16),
dat_r=Signal(16), re=Signal(),
dat_w=Signal(16), we=Signal())
ext_port = DummyExtPort()

r_insn = Signal(16)
r_pc = Signal(mem_port.adr.nbits, reset=reset_addr)
@@ -48,7 +55,7 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
i_type2 = s_insn[0:2]
i_shift = s_insn[1:5]
i_imm5 = s_insn[0:5]
i_imm7 = s_insn[0:8]
i_imm8 = s_insn[0:8]
i_imm11 = s_insn[0:11]
i_regX = s_insn[2:5]
i_regY = s_insn[5:8]
@@ -103,15 +110,15 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):

self.submodules.fsm = FSM(reset_state="FETCH")
self.comb += [
s_insn.eq(Mux(self.fsm.ongoing("LOAD/JUMP"), mem_port.dat_r, r_insn))
s_insn.eq(Mux(self.fsm.ongoing("DECODE/LOAD/JUMP"), mem_port.dat_r, r_insn))
]
self.fsm.act("FETCH",
mem_port.adr.eq(r_pc),
mem_port.re.eq(1),
NextValue(r_pc, r_pc + 1),
NextState("LOAD/JUMP")
NextState("DECODE/LOAD/JUMP")
)
self.fsm.act("LOAD/JUMP",
self.fsm.act("DECODE/LOAD/JUMP",
NextValue(r_insn, mem_port.dat_r),
If(i_clsA,
mem_port.adr.eq(Cat(i_regX, r_win)),
@@ -129,10 +136,19 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
).Else(
NextState("M-READ")
)
# ).Elif(i_clsI,
# mem_port.adr.eq(Cat(i_regZ, r_win)),
# mem_port.re.eq(1),
# NextState("?-I")
).Elif(i_clsI,
mem_port.adr.eq(Cat(i_regZ, r_win)),
mem_port.re.eq(1),
Case(Cat(i_code3, C(OPCLASS_I, 2)), {
OPCODE_MOVL: NextState("I-EXECUTE-MOVx/ADDI"),
OPCODE_MOVH: NextState("I-EXECUTE-MOVx/ADDI"),
OPCODE_MOVA: NextState("I-EXECUTE-MOVx/ADDI"),
OPCODE_ADDI: NextState("I-EXECUTE-MOVx/ADDI"),
# OPCODE_LDI: NextState(),
# OPCODE_STI: NextState(),
# OPCODE_JAL: NextState(),
# OPCODE_JR: NextState(),
})
).Elif(i_clsC,
If(s_cond == i_flag,
NextValue(r_pc, AddSignedImm(r_pc, i_imm11))
@@ -224,6 +240,17 @@ def __init__(self, reset_addr, mem_port, ext_port=None, simulation=False):
ext_port.we.eq(i_ext),
NextState("FETCH")
)
self.fsm.act("I-EXECUTE-MOVx/ADDI",
mem_port.adr.eq(Cat(i_regZ, r_win)),
Case(Cat(i_code2, C(0, 1), C(OPCLASS_I, 2)), {
OPCODE_MOVL: mem_port.dat_w.eq(Cat(i_imm8, C(0, 8))),
OPCODE_MOVH: mem_port.dat_w.eq(Cat(C(0, 8), i_imm8)),
OPCODE_MOVA: mem_port.dat_w.eq(AddSignedImm(r_pc, i_imm8)),
OPCODE_ADDI: mem_port.dat_w.eq(AddSignedImm(mem_port.dat_r, i_imm8)),
}),
mem_port.we.eq(1),
NextState("FETCH")
)
self.fsm.act("HALT",
NextState("HALT")
)
@@ -255,7 +282,7 @@ def do_finalize(self):
ext_port = self.ext.get_port(has_re=True, write_capable=True)
self.specials += ext_port
else:
ext_port = None
ext_port = DummyExtPort()

self.submodules.dut = BonelessCore(reset_addr=8,
mem_port=mem_port,
@@ -267,7 +294,7 @@ class BonelessTestCase(unittest.TestCase):
def setUp(self):
self.tb = BonelessTestbench()

def configure(self, tb, regs, code, data=[], extr=[]):
def configure(self, tb, code, regs=[], data=[], extr=[]):
tb.mem_init = [*regs, *[0] * (8 - len(regs))] + assemble(code + [J(-1024)] + data)
tb.ext_init = extr

@@ -424,3 +451,39 @@ def test_STX(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x0001)
yield from self.assertExternal(tb, 1, 0x1234)

@simulation_test(regs=[0xabcd],
code=[MOVL(R0, 0x12)])
def test_MOVL(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x0012)

@simulation_test(regs=[0xabcd],
code=[MOVH(R0, 0x12)])
def test_MOVH(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x1200)

@simulation_test(regs=[0xabcd],
code=[MOVA(R0, 1)])
def test_MOVA(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x000a)

@simulation_test(regs=[1234, 1234],
code=[ADDI(R0, +42),
ADDI(R1, -42)])
def test_ADDI(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 1234+42)
yield from self.assertMemory(tb, 1, 1234-42)

@simulation_test(regs=[0xabcd, 0xabcd],
code=[MOVI(R0, 0x12),
MOVI(R1, 0x1234),
MOVI(R2, 0x89ab)])
def test_MOVI(self, tb):
yield from self.run_core(tb)
yield from self.assertMemory(tb, 0, 0x0012)
yield from self.assertMemory(tb, 1, 0x1234)
yield from self.assertMemory(tb, 2, 0x89ab)