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base repository: m-labs/nmigen
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  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Dec 12, 2018

  1. ClockDomain.{rst→reset}, for consistency with ResetInserter.

    nmigen.compat.ClockDomain would alias this, for Migen compatibility.
    whitequark committed Dec 12, 2018
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    851ed06 View commit details
Showing with 7 additions and 7 deletions.
  1. +2 −2 examples/arst.py
  2. +1 −1 nmigen/back/rtlil.py
  3. +3 −3 nmigen/fhdl/cd.py
  4. +1 −1 nmigen/fhdl/ir.py
4 changes: 2 additions & 2 deletions examples/arst.py
Original file line number Diff line number Diff line change
@@ -17,5 +17,5 @@ def get_fragment(self, platform):
sys = ClockDomain(async_reset=True)
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys}))
# print(rtlil.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))
2 changes: 1 addition & 1 deletion nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -445,7 +445,7 @@ def _convert_stmts(case, stmts):
cd = clock_domains[cd_name]
triggers.append(("posedge", xformer(cd.clk)))
if cd.async_reset:
triggers.append(("posedge", xformer(cd.rst)))
triggers.append(("posedge", xformer(cd.reset)))

for trigger in triggers:
with process.sync(*trigger) as sync:
6 changes: 3 additions & 3 deletions nmigen/fhdl/cd.py
Original file line number Diff line number Diff line change
@@ -27,7 +27,7 @@ class ClockDomain:
clk : Signal, inout
The clock for this domain. Can be driven or used to drive other signals (preferably
in combinatorial context).
rst : Signal or None, inout
reset : Signal or None, inout
Reset signal for this domain. Can be driven or used to drive.
"""
def __init__(self, name=None, reset_less=False, async_reset=False):
@@ -41,8 +41,8 @@ def __init__(self, name=None, reset_less=False, async_reset=False):

self.clk = Signal(name=self.name + "_clk")
if reset_less:
self.rst = None
self.reset = None
else:
self.rst = Signal(name=self.name + "_rst")
self.reset = Signal(name=self.name + "_reset")

self.async_reset = async_reset
2 changes: 1 addition & 1 deletion nmigen/fhdl/ir.py
Original file line number Diff line number Diff line change
@@ -53,7 +53,7 @@ def add_subfragment(self, subfragment, name=None):
def prepare(self, ports, clock_domains):
from .xfrm import ResetInserter

resets = {cd.name: cd.rst for cd in clock_domains.values() if cd.rst is not None}
resets = {cd.name: cd.reset for cd in clock_domains.values() if cd.reset is not None}
frag = ResetInserter(resets)(self)

self_driven = union(s._lhs_signals() for s in self.statements)