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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: aab01d9e5912
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 12, 2018

  1. Copy the full SHA
    c05c189 View commit details
  2. fhdl.ast.Signal: implement attrs field.

    whitequark committed Dec 12, 2018
    Copy the full SHA
    aab01d9 View commit details
Showing with 22 additions and 7 deletions.
  1. +8 −0 nmigen/back/rtlil.py
  2. +8 −1 nmigen/fhdl/ast.py
  3. +6 −6 nmigen/genlib/cdc.py
8 changes: 8 additions & 0 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -62,6 +62,12 @@ def __exit__(self, *args):
self._append("end\n")
self.rtlil._buffer.write(str(self))

def attribute(self, name, value):
if isinstance(value, str):
self._append("attribute \\{} \"{}\"\n", name, value.replace("\"", "\\\""))
else:
self._append("attribute \\{} {}\n", name, int(value))

def wire(self, width, port_id=None, port_kind=None, name=None, src=""):
self._src(src)
name = self._make_name(name, local=False)
@@ -260,6 +266,8 @@ def on_Signal(self, node):
wire_name = "{}_{}".format(self.sub_name, node.name)
else:
wire_name = node.name
for attr_name, attr_value in node.attrs.items():
self.rtlil.attribute(attr_name, attr_value)
wire_curr = self.rtlil.wire(width=node.nbits, name=wire_name,
port_id=port_id, port_kind=port_kind)
if node in self.driven:
9 changes: 8 additions & 1 deletion nmigen/fhdl/ast.py
Original file line number Diff line number Diff line change
@@ -502,16 +502,21 @@ class Signal(Value, DUID):
If `bits_sign` is `None`, the signal bit width and signedness are
determined by the integer range given by `min` (inclusive,
defaults to 0) and `max` (exclusive, defaults to 2).
attrs : dict
Dictionary of synthesis attributes.
Attributes
----------
nbits : int
signed : bool
name : str
reset : int
reset_less : bool
attrs : dict
"""

def __init__(self, bits_sign=None, name=None, reset=0, reset_less=False, min=None, max=None):
def __init__(self, bits_sign=None, name=None, reset=0, reset_less=False, min=None, max=None,
attrs=None):
super().__init__()

if name is None:
@@ -546,6 +551,8 @@ def __init__(self, bits_sign=None, name=None, reset=0, reset_less=False, min=Non
self.reset = reset
self.reset_less = reset_less

self.attrs = OrderedDict(() if attrs is None else attrs)

def bits_sign(self):
return self.nbits, self.signed

12 changes: 6 additions & 6 deletions nmigen/genlib/cdc.py
Original file line number Diff line number Diff line change
@@ -4,19 +4,19 @@
__all__ = ["MultiReg"]


class MultiReg(Module):
class MultiReg:
def __init__(self, i, o, odomain="sys", n=2, reset=0):
self.i = i
self.o = o
self.odomain = odomain

self.regs = [Signal(self.i.bits_sign(), name="cdc{}".format(i),
reset=reset, reset_less=True)#, attrs=("no_retiming",))
for i in range(n)]
self._regs = [Signal(self.i.bits_sign(), name="cdc{}".format(i),
reset=reset, reset_less=True, attrs={"no_retiming": True})
for i in range(n)]

def get_fragment(self, platform):
f = Module()
for i, o in zip((self.i, *self.regs), self.regs):
for i, o in zip((self.i, *self._regs), self._regs):
f.sync[self.odomain] += o.eq(i)
f.comb += self.o.eq(self.regs[-1])
f.comb += self.o.eq(self._regs[-1])
return f.lower(platform)