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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: ad9b45adcd44
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Dec 12, 2018

  1. fhdl.ir: fix port threading code.

    whitequark committed Dec 12, 2018
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    ad9b45a View commit details
Showing with 2 additions and 2 deletions.
  1. +1 −1 examples/alu_hier.py
  2. +1 −1 nmigen/fhdl/ir.py
2 changes: 1 addition & 1 deletion examples/alu_hier.py
Original file line number Diff line number Diff line change
@@ -56,4 +56,4 @@ def get_fragment(self, platform):
alu = ALU(width=16)
frag = alu.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o, alu.add.o, alu.sub.o]))
print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
2 changes: 1 addition & 1 deletion nmigen/fhdl/ir.py
Original file line number Diff line number Diff line change
@@ -66,7 +66,7 @@ def prepare(self, ports, clock_domains):
subfrag, sub_ins, sub_outs = subfrag.prepare(ports=self_used | ports,
clock_domains=clock_domains)
frag.subfragments[n] = (subfrag, name)
ins |= sub_ins - self_driven
ins -= sub_outs
outs |= ports & sub_outs

frag.add_ports(ins, outs)