Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 851ed06769c5
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 263d57732319
Choose a head ref
  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 12, 2018

  1. Copy the full SHA
    6d5878a View commit details
  2. Copy the full SHA
    1d46ffb View commit details
  3. fhdl.ast.Signal: implement reset_less signals.

    whitequark committed Dec 12, 2018
    Copy the full SHA
    263d577 View commit details
Showing with 17 additions and 3 deletions.
  1. +10 −2 nmigen/fhdl/ast.py
  2. +6 −0 nmigen/fhdl/dsl.py
  3. +1 −1 nmigen/fhdl/xfrm.py
12 changes: 10 additions & 2 deletions nmigen/fhdl/ast.py
Original file line number Diff line number Diff line change
@@ -492,6 +492,10 @@ class Signal(Value, DUID):
domain is reset, the ``Signal`` assumes the given value. When this ``Signal`` is unassigned
in combinatorial context (due to conditional assignments not being taken), the ``Signal``
assumes its ``reset`` value. Defaults to 0.
reset_less : bool
If ``True``, do not generate reset logic for this ``Signal`` in synchronous statements.
The ``reset`` value is only used as a combinatorial default or as the initial value.
Defaults to ``False``.
Attributes
----------
@@ -501,11 +505,14 @@ class Signal(Value, DUID):
reset : int
"""

def __init__(self, bits_sign=1, reset=0, name=None):
def __init__(self, bits_sign=1, name=None, reset=0, reset_less=False):
super().__init__()

if name is None:
name = tracer.get_var_name()
try:
name = tracer.get_var_name()
except tracer.NameNotFound:
name = "$signal"
self.name = name

if isinstance(bits_sign, int):
@@ -514,6 +521,7 @@ def __init__(self, bits_sign=1, reset=0, name=None):
if not isinstance(self.nbits, int) or self.nbits < 0:
raise TypeError("Width must be a positive integer")
self.reset = reset
self.reset_less = reset_less

def bits_sign(self):
return self.nbits, self.signed
6 changes: 6 additions & 0 deletions nmigen/fhdl/dsl.py
Original file line number Diff line number Diff line change
@@ -38,11 +38,17 @@ def __iadd__(self, assigns):
def __getattr__(self, name):
return _ModuleBuilderSyncCD(self._builder, self._depth, name)

def __getitem__(self, name):
return self.__getattr__(name)

def __setattr__(self, name, value):
if not isinstance(value, _ModuleBuilderSyncCD):
raise AttributeError("Cannot assign sync.{} attribute - use += instead"
.format(name))

def __setitem__(self, name, value):
return self.__setattr__(name, value)


class _ModuleBuilderRoot:
def __init__(self, builder, depth):
2 changes: 1 addition & 1 deletion nmigen/fhdl/xfrm.py
Original file line number Diff line number Diff line change
@@ -114,7 +114,7 @@ def _wrap_control(self, fragment, cd_name, signals):

class ResetInserter(_ControlInserter):
def _wrap_control(self, fragment, cd_name, signals):
stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals]
stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals if not s.reset_less]
fragment.add_statements(Switch(self.controls[cd_name], {1: stmts}))