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base repository: whitequark/glasgow
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base: 8806951c545a
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head repository: whitequark/glasgow
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compare: efb6bc65fc18
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  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on Dec 5, 2018

  1. Copy the full SHA
    efb6bc6 View commit details
Showing with 23 additions and 6 deletions.
  1. +19 −3 software/glasgow/cli.py
  2. +3 −2 software/glasgow/device/hardware.py
  3. +1 −1 software/glasgow/target/hardware.py
22 changes: 19 additions & 3 deletions software/glasgow/cli.py
Original file line number Diff line number Diff line change
@@ -170,15 +170,23 @@ def add_voltage_arg(parser, help):
add_voltage_arg(p_voltage_limit,
help="maximum allowed I/O port voltage")

def add_toolchain_args(parser):
parser.add_argument(
"--synthesis-opts", metavar="OPTIONS", type=str, default="",
help="(advanced) pass OPTIONS to FPGA synthesis toolchain")

p_run = subparsers.add_parser(
"run", formatter_class=TextHelpFormatter,
help="load an applet bitstream and run applet code")
add_toolchain_args(p_run)

p_run.add_argument(
"--rebuild", default=False, action="store_true",
help="rebuild bitstream even if an identical one is already loaded")
p_run.add_argument(
"--trace", metavar="FILENAME", type=argparse.FileType("wt"), default=None,
help="trace applet I/O to FILENAME")

g_run_bitstream = p_run.add_mutually_exclusive_group(required=True)
g_run_bitstream.add_argument(
"--bitstream", metavar="FILENAME", type=argparse.FileType("rb"),
@@ -193,6 +201,7 @@ def add_voltage_arg(parser, help):
p_flash = subparsers.add_parser(
"flash", formatter_class=TextHelpFormatter,
help="program FX2 firmware or applet bitstream into EEPROM")
add_toolchain_args(p_flash)

g_flash_firmware = p_flash.add_mutually_exclusive_group()
g_flash_firmware.add_argument(
@@ -226,6 +235,8 @@ def serial(arg):
p_build = subparsers.add_parser(
"build", formatter_class=TextHelpFormatter,
help="(advanced) build applet logic and save it as a file")
add_toolchain_args(p_build)

p_build.add_argument(
"--trace", default=False, action="store_true",
help="include applet analyzer")
@@ -328,6 +339,10 @@ def create_logger(args):
root_logger.setLevel(level)


def _toolchain_opts(args):
return {"debug": True, "synth_opts": args.synthesis_opts}


async def _main():
args = get_argparser().parse_args()
create_logger(args)
@@ -384,7 +399,8 @@ async def _main():
target, applet = _applet(args)
device.demultiplexer = DirectDemultiplexer(device)

await device.download_target(target, rebuild=args.rebuild)
await device.download_target(target, rebuild=args.rebuild,
toolchain_opts=_toolchain_opts(args))

if args.trace:
logger.info("starting applet analyzer")
@@ -521,7 +537,7 @@ async def run_applet():
logger.info("building bitstream for applet %s", args.applet)
target, applet = _applet(args)
new_bitstream_id = target.get_bitstream_id()
new_bitstream = target.get_bitstream(debug=True)
new_bitstream = target.get_bitstream(**_toolchain_opts(args))

# We always build and reflash the bitstream in case the one currently
# in EEPROM is corrupted. If we only compared the ID, there would be
@@ -583,7 +599,7 @@ async def run_applet():
if args.type in ("bin", "bitstream"):
logger.info("building bitstream for applet %r", args.applet)
with open(args.filename or args.applet + ".bin", "wb") as f:
f.write(target.get_bitstream(debug=True))
f.write(target.get_bitstream(**_toolchain_opts(args)))
if args.type in ("zip", "archive"):
logger.info("building archive for applet %r", args.applet)
with target.get_build_tree() as tree:
5 changes: 3 additions & 2 deletions software/glasgow/device/hardware.py
Original file line number Diff line number Diff line change
@@ -304,13 +304,14 @@ async def download_bitstream(self, bitstream, bitstream_id=b"\xff" * 16):
except usb1.USBErrorPipe:
raise GlasgowDeviceError("FPGA configuration failed")

async def download_target(self, target, debug=True, rebuild=False):
async def download_target(self, target, rebuild=False, toolchain_opts={}):
bitstream_id = target.get_bitstream_id()
if await self.bitstream_id() == bitstream_id and not rebuild:
logger.info("device already has bitstream ID %s", bitstream_id.hex())
else:
logger.info("building bitstream ID %s", bitstream_id.hex())
await self.download_bitstream(target.get_bitstream(debug=True), bitstream_id)
bitstream = target.get_bitstream(**toolchain_opts)
await self.download_bitstream(bitstream, bitstream_id)

async def _iobuf_enable(self, on):
await self.control_write(usb1.REQUEST_TYPE_VENDOR, REQ_IOBUF_ENABLE, on, 0, [])
2 changes: 1 addition & 1 deletion software/glasgow/target/hardware.py
Original file line number Diff line number Diff line change
@@ -111,7 +111,7 @@ def get_bitstream(self, build_dir=None, debug=False, **kwargs):
if build_dir is None:
build_dir = tempfile.mkdtemp(prefix="glasgow_")
try:
self.build(build_dir=build_dir)
self.build(build_dir=build_dir, **kwargs)
with open(os.path.join(build_dir, "top.bin"), "rb") as f:
bitstream = f.read()
if debug: