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base repository: m-labs/nmigen-boards
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head repository: m-labs/nmigen-boards
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compare: bb52dfb9575c
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  • 1 commit
  • 6 files changed
  • 1 contributor

Commits on Jun 6, 2019

  1. Factor out SPI flash resource definition.

    whitequark committed Jun 6, 2019
    Copy the full SHA
    bb52dfb View commit details
Showing with 58 additions and 43 deletions.
  1. +1 −0 nmigen_boards/dev/__init__.py
  2. +36 −0 nmigen_boards/dev/flash.py
  3. +5 −6 nmigen_boards/ice40_hx1k_blink_evn.py
  4. +6 −15 nmigen_boards/icebreaker.py
  5. +5 −6 nmigen_boards/icestick.py
  6. +5 −16 nmigen_boards/tinyfpga_bx.py
1 change: 1 addition & 0 deletions nmigen_boards/dev/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
from .flash import SPIFlashResources
36 changes: 36 additions & 0 deletions nmigen_boards/dev/flash.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
from nmigen.build import *


__all__ = ["SPIFlashResources"]


def SPIFlashResources(number, *, cs_n, clk, mosi, miso, wp_n=None, hold_n=None, attrs=None):
resources = []

io_all = []
if attrs is not None:
io_all.append(attrs)
io_all.append(Subsignal("cs_n", Pins(cs_n, dir="o")))
io_all.append(Subsignal("clk", Pins(clk, dir="o")))

io_1x = list(io_all)
io_1x.append(Subsignal("mosi", Pins(mosi, dir="o")))
io_1x.append(Subsignal("miso", Pins(miso, dir="i")))
if wp_n is not None and hold_n is not None:
# Tristate these pins by default, and rely on a pullup on the board or within the flash.
# An alternative would be to define them as outputs with reset value of 1, but that's
# not currently possible in nMigen.
io_1x.append(Subsignal("wp_n", Pins(wp_n, dir="oe")))
io_1x.append(Subsignal("hold_n", Pins(hold_n, dir="oe")))
resources.append(Resource("spiflash", number, *io_1x))

io_2x = list(io_all)
io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io")))
resources.append(Resource("spiflash2x", number, *io_2x))

if wp_n is not None and hold_n is not None:
io_4x = list(io_all)
io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp_n, hold_n]), dir="io")))
resources.append(Resource("spiflash4x", number, *io_4x))

return resources
11 changes: 5 additions & 6 deletions nmigen_boards/ice40_hx1k_blink_evn.py
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *


__all__ = ["ICE40HX1KBlinkEVNPlatform"]
@@ -25,12 +26,10 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
Resource("user_btn", 2, Pins("54"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_btn", 3, Pins("52"), Attrs(IO_STANDARD="SB_LVCMOS33")),

Resource("spiflash", 0,
Subsignal("cs_n", Pins("49", dir="o")),
Subsignal("clk", Pins("48", dir="o")),
Subsignal("mosi", Pins("45", dir="o")),
Subsignal("miso", Pins("46", dir="i")),
Attrs(IO_STANDARD="SB_LVCMOS33")
*SPIFlashResources(0,
cs_n="49", clk="48",
mosi="45", miso="46",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
21 changes: 6 additions & 15 deletions nmigen_boards/icebreaker.py
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *


__all__ = ["ICEBreakerPlatform"]
@@ -28,21 +29,11 @@ class ICEBreakerPlatform(LatticeICE40Platform):
Attrs(IO_STANDARD="SB_LVTTL")
),

Resource("spiflash", 0,
Subsignal("cs_n", Pins("16", dir="o")),
Subsignal("clk", Pins("15", dir="o")),
Subsignal("mosi", Pins("14", dir="o")),
Subsignal("miso", Pins("17", dir="i")),
Subsignal("wp", Pins("12", dir="o")),
Subsignal("hold", Pins("13", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS33")
),

Resource("spiflash4x", 0,
Subsignal("cs_n", Pins("16", dir="o")),
Subsignal("clk", Pins("15", dir="o")),
Subsignal("dq", Pins("14 17 12 13", dir="io")),
Attrs(IO_STANDARD="SB_LVCMOS33")
*SPIFlashResources(0,
cs_n="16", clk="15",
mosi="14", miso="17",
wp_n="12", hold_n="13",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
11 changes: 5 additions & 6 deletions nmigen_boards/icestick.py
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *


__all__ = ["ICEStickPlatform"]
@@ -39,12 +40,10 @@ class ICEStickPlatform(LatticeICE40Platform):
Attrs(IO_STANDARD="SB_LVCMOS33")
),

Resource("spiflash", 0,
Subsignal("cs_n", Pins("71", dir="o")),
Subsignal("clk", Pins("70", dir="o")),
Subsignal("mosi", Pins("67", dir="o")),
Subsignal("miso", Pins("68", dir="i")),
Attrs(IO_STANDARD="SB_LVCMOS33")
*SPIFlashResources(0,
cs_n="71", clk="70",
mosi="67", miso="68",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
21 changes: 5 additions & 16 deletions nmigen_boards/tinyfpga_bx.py
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *


__all__ = ["TinyFPGABXPlatform"]
@@ -24,22 +25,10 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
Attrs(IO_STANDARD="SB_LVCMOS33")
),

Resource("spiflash", 0,
Subsignal("cs_n", Pins("F7", dir="o")),
Subsignal("clk", Pins("G7", dir="o")),
Subsignal("mosi", Pins("G6", dir="o")),
Subsignal("miso", Pins("H7", dir="i")),
Subsignal("wp", Pins("H4", dir="o")),
Subsignal("hold", Pins("J8", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS33")
),

Resource("spiflash4x", 0,
Subsignal("cs_n", Pins("F7", dir="o")),
Subsignal("clk", Pins("G7", dir="o")),
Subsignal("dq", Pins("G6 H7 H4 J8", dir="io")),
Attrs(IO_STANDARD="SB_LVCMOS33")
),
*SPIFlashResources(0,
cs_n="F7", clk="G7",
mosi="G6", miso="H7", wp_n="H4", hold_n="J8",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
]
connectors = [
Connector("gpio", 0,