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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 2b3a0e9fa044
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jun 7, 2019

  1. vendor.xilinx_7series: fix typos.

    Jean-François Nguyen authored and whitequark committed Jun 7, 2019
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    2b3a0e9 View commit details
Showing with 2 additions and 2 deletions.
  1. +2 −2 nmigen/vendor/xilinx_7series.py
4 changes: 2 additions & 2 deletions nmigen/vendor/xilinx_7series.py
Original file line number Diff line number Diff line change
@@ -63,7 +63,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
add_files {{name}}.v
read_xdc {{name}}.xdc
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
synth_design -top {{name}} -part {{platform.device}}
synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speedgrade}}
{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
report_timing_summary -file {{name}}_timing_synth.rpt
report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
@@ -100,8 +100,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_ports {{signal.name}}]
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
"""
}
command_templates = [