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Lib FIFO: RTLIL with syntax error #162

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ydnatag opened this issue Jul 28, 2019 · 1 comment
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Lib FIFO: RTLIL with syntax error #162

ydnatag opened this issue Jul 28, 2019 · 1 comment
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@ydnatag
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ydnatag commented Jul 28, 2019

Hello

I'm doing some AXI cores using nMigen (https://github.com/andresdemski/nmigen-axi/blob/master/nmigen-axi/axi_stream/fifo.py) and i found a syntax error in the RTLIL file while i was trying to generate a verilog file.

The error message was: nmigen.back.verilog.YosysError: ERROR: Parser error in line 509: syntax error

I generated the RTLIL and i check the line 509:

495   attribute \src "/home/ademski/Documents/opensource/nmigen/nmigen/lib/fifo.py:349"
496   cell $add $30
497     parameter \A_SIGNED 0
498     parameter \A_WIDTH 5
499     parameter \B_SIGNED 0
500     parameter \B_WIDTH 1
501     parameter \Y_WIDTH 6
502     connect \A \consume_r_bin
503     connect \B $27
504     connect \Y $29
505   end
506   connect $26 $29
507   process $group_13
508     assign \storage_r_addr 4'0000
509     assign \storage_r_addr $26 [4:0] [3:0]
510     sync init
511   end

The syntax error was generated by:

rdport.addr.eq((consume_r_bin + do_read)[:-1]),

I suppose that [4:0] [3:0] is interpreted as double indexing and not truncation as it is expected.

nMigen commit: 5fd8a79
yosys version: yosys-0.8-1

Regards
Andres

@whitequark
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This was a bug in Yosys that was fixed in commit YosysHQ/yosys@4effb38. You need to use Yosys master, see README. (Yosys 0.9 when it is released will also work.)

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