platform output bus bits in separate modules causes AssertionError #190
Comments
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Reduced testcase: from nmigen import *
from nmigen.build import *
from nmigen.vendor.xilinx_7series import *
class se(Elaboratable):
def __init__(self, p):
self.p = p
def elaborate(self, platform):
m = Module()
m.submodules.obuf = Instance("blah", o_O=self.p)
return m
class Synthesizer(Elaboratable):
def elaborate(self, platform):
m = Module()
d = platform.request("bus", 0)
for i in range(len(d)):
m.submodules["dacbit{}".format(i)] = se(d[i])
return m
class SynthDigital1Platform(Xilinx7SeriesPlatform):
device = "xc7a15t"
package = "ftg256"
speed = "1"
resources = [
Resource("bus", 0, Pins("A8 B9 B10 B12 B15 C16 D14 E16 F15 G14 H16 J15", dir="o")),
]
connectors = []
if __name__ == "__main__":
SynthDigital1Platform().build(Synthesizer(), do_program=False) |
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By the way, why are you adding a "fake clock"? It's not necessary to have a default clock unless your code explicitly relies on it, you just need to make your own |
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The fake clock is now gone. I hadn't quite figured out how clock domains worked when I wrote that. |
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Ah, yeah. Documentation for that needs to be improved. |
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I'll fix this, but this might require a fairly significant redesign of use-def tracking (to make it per-bit rather than per-signal), so the fix is unlikely to be quick. |
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I have implemented a fairly clean workaround. I mostly thought I'd report it for the sake of other users. I started with nMigen a bit over a week ago and have converted two FPGA designs so far. It's a huge improvement over Verilog in many ways. Thanks for this great tool. |
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You're welcome! That sounds like many of my goals when making nMigen have been achieved. |
I've worked around this by putting output buffer instances (OBUFTDS) for all 12 bits in the bus in a single module. It was failing when I used a module per output bit containing the buffer and serializer.
Gist of code to reproduce:
https://gist.github.com/dlharmon/94f9b04b5d0bcf6dcd4a1bed1e194c0b
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